DS2152 datasheet(74/97 Pages) MAXIM

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DS2152

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14 TRANSMIT TRANSPARENCY

Each of the 24 T1 channels in the transmit direction of the DS2152 can be either forced to be transparent

or, in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data

in the channels. Transparency can be invoked on a channel-by-channel basis by properly setting the

TTR1, TTR2, and TTR3 registers.

TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER

(Address = 39 to 3B Hex)

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

TTR1 (39)

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

TTR2 (3A)

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

TTR3 (3B)

SYMBOL

POSITION

NAME AND DESCRIPTION

CH24

TTR3.7

Transmit Transparency Registers.

0 = this DS0 channel is not transparent

CH1

TTR1.0

1 = this DS0 channel is transparent

Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0

channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or

clear). If a DS0 is programmed to be clear, no robbed-bit signaling will be inserted nor will the channel

have Bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a

Yellow Alarm is transmitted. Also, the user has the option to prevent the TTR registers from determining

which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all

24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are

programmed. In this manner, the TTR registers are only affecting which channels are to have robbed-bit

signaling inserted into them. See Figure 16-11 for more details.

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