Z84C90

KIO Serial/Parallel Counter Timer

PS011802-0902

5

Figure 3. 100-Pin LQFP Configuration

Pin Descriptions

A0–A3. Address bus (inputs). Used to select the port/register for each bus cycle.

ARDY, BRDY. Port Ready (outputs, Active High). These signals indicate that the port is

ready for a data transfer. In Mode 0, the signal indicates that the port has data available to

the peripheral device. In Mode 1, the signal indicates that the port is ready to accept data

from the peripheral device. In Mode 2, ARDY indicates that Port A has data available for

the peripheral device, but that the data is not be placed onto PA0–PA7 until the ASTB sig-

nal is Active. BRDY indicates that Port A is able to accept data from a peripheral device.

100-Pin LQFP

1

5

10

15

20

25

26

30

35

40

45

50

51

55

60

65

70

75

76

80

85

90

95

100

NC

NC

GND

GND

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

BRDY

BSTB

ARDY

ASTB

ZC/TO3

ZC/TO2

ZC/TO1

ZC/TO0

IE1

IE0

NC

NC

NC

NC

PC0 (WT/RDYB)

GND

CSTA

DCDA

DCDB

CTSB

TxDB

TxCB

RxCB

RxDB

A0

A1

A2

A3

CS

M1

RD

IORQ

RESET

CLK/TRG3

NC

NC