Z84C90

KIO Serial/Parallel Counter Timer

PS011802-0902

7

IEI. Interrupt Enable In (input, Active High). This signal is used with Interrupt Enable

Out (IEO) to form a priority daisy chain when there is more than one interrupt-driven

device. A High on this line indicates that no higher-priority device is requesting an inter-

rupt.

IEO. Interrupt Enable Out (output, Active High). This signal is used with Interrupt Enable

In (IEI) to form a priority daisy chain when there is more than one interrupt-driven device.

A High on this line indicates that this device is requesting an interrupt, and that no higher-

priority device, is not requesting an interrupt. A Low blocks any lower-priority devices

from requesting an interrupt.

to transfer data between the KIO and the CPU. When IORQ, RD, and CS are Active Low,

When IORQ and M1 are both Active Low, the KIO may respond with an interrupt vector

from its highest-priority interrupting device.

M1. Machine Cycle 1 (input, Active Low). When M1 and RD are Low, the Z80 CPU

fetches an instruction from memory; the KIO decodes this cycle to determine if the RETI

instruction sequence is being executed. When M1 and IORQ are both active, the KIO

decodes the cycle to be an interrupt acknowledge, and may respond with a vector from its

highest-priority interrupting device.

OSC. Oscillator (output). This output is a reference clock for the oscillator.

the least-significant bit of the bus.

the least-significant bit of the bus. This port can also supply 1.5mA at 1.5V to drive Dar-

lington transistors.

These pins are multiplexed between the 8-bit PIA and additional modem control signals

for the serial channels.

RD. Read (input, Active Low). When RD is active, a memory or I/O read operation is in

CPU.

RESET. Reset (input, Active Low). A Low on this pin forces the KIO into a Reset condi-

tion. This signal must be active for a minimum of three Clock cycles. The KIO resets so

that the PIO ports operate in Mode 1