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MPC8560CPX667JC Datasheet(PDF) 15 Page - NXP Semiconductors |
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MPC8560CPX667JC Datasheet(HTML) 15 Page - NXP Semiconductors |
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15 / 108 page ![]() MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 15 Clock Timing 4 Clock Timing 4.1 System Clock Timing Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8560. TDMA or TDMB Nibble mode — 10 — — mW 7 Per channel — 5 — — Notes: 1. GVDD=2.5, ECC enabled, 66% bus utilization, 33% write cycles, 10pF load on data, 10pF load on address/command, 10pF load on clock 2. OVDD=3.3, 30pF load per pin, 54% bus utilization, 33% write cycles 3. OVDD=3.3, 25pF load per pin, 5pF load on clock, 40% bus utilization, 33% write cycles 4. VDD=1.2, OVDD=3.3 5. LVDD=2.5/3.3, 15pF load per pin, 25% bus utilization 6. Power dissipation for one TSEC only 7. OVDD=3.3, 10pF load per pin, 50% bus utilization Table 7. SYSCLK AC Timing Specifications Parameter/Condition Symbol Min Typical Max Unit Notes SYSCLK frequency fSYSCLK — — 166 MHz 1 SYSCLK cycle time tSYSCLK 6.0 — — ns — SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns 2 SYSCLK duty cycle tKHKL/tSYSCLK 40 — 60 % 3 SYSCLK jitter — — — +/- 150 ps 4, 5 Notes: 1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation regardless of the input frequency. Table 6. Estimated Typical I/O Power Consumption (continued) Interface Parameter GVDD (2.5 V) OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Units Notes |
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