W5300 datasheet(9/128 Pages) WIZNET

9 / 128 page

PLL(Phase-Locked Loop)

It creates a 150MHz clock signal by multiplying 25MHz clock source by six. The 150MHz clock

is used for operating internal blocks such as TCP/IP core block,

‘Host Interface Manager’ and

‘Register Manager’. PLL is locked-in after reset and it supplies a stable clock.

Power Regulator

With 3.3V power input, the power regulator creates 1.8V/150mA power. This power regulator

supplies the power for core operation of W5300. It is not required to add other power regulators,

but recommended to add a capacitor for more stable 1.8V power supplying.

Host Interface Manager

It detects host bus signal, and manages read/write operations of the host according to data bus

width or host interface mode.

It manages Mode register, COMMON Register, and SOCKET Register.

Memory Manager

It manages internal data memory of 128KBytes

– TX/RX memory allocated in each SOCKET by

the host. The host can access the memory only through TX/RX FIFO Register of each SOCKET.

128KB TX/RX DPRAM

It is the 128KByte memory for data communication and composed of 16 DPRAM(Dual-Port

RAM) of 8KBytes. It is allocated flexibly to each SOCKET by the host.

MII(Media Independent Interface) Manager

It manages MII interface. MII interface can be switched to internal PHY or external PHY(3rd party

PHY) according to the configuration of TEST_MODE[3:0].

Internal Ethernet PHY

W5300 includes 10BaseT/100BaseTX Ethernet PHY. Internal PHY supports half-duplex/full

duplex, auto-negotiation and auto MDI/MDIX. It also supports 6 network indicator LED output

such as Link status, speed and duplex.

TCP/IP Core

TCP/IP Core is the fully hardwired logic based on network protocol processing technology of

WIZnet.

W5300 Datasheet(PDF) 9 Page - WIZnet Co., Ltd