TMUX646

MIPI Switch

VDD

2.2 µF

100 nF

Processor

MIPI Module 1

MIPI Module 2

SEL

/OE

Trio[1:3]

Trio [1:3]

Trio[1:3]

50

Ω

50

Ω

50

Ω

1.5 V to 5.5 V

Figure 9-2. Typical C-PHY Application

9.2.1 Design Requirements

Design requirements of the MIPI standard must be followed. Supply pin decoupling capacitors of 2.2 µF and 100

nF are recommended for best performance. The TMUX646 has internal 6-MΩ pulldown resistors on SEL and

OE. The pulldown on these pins ensure that the digital remains in a non-floating state during system power-up to

prevent shoot through current spikes and an unknown switch status. By default the switch will power up enabled

and with the A path selected until driven externally by the processor.

9.2.2 Detailed Design Procedure

The TMUX646 can be properly operated without any external components. However, TI recommends that

unused I/O signal pins be connected to ground through a 50 Ω resistor to prevent signal reflections and maintain

device performance. The NC pins of the device do not require any external connections or terminations and

have no connection to the rest of the device internally.

The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the

application. For example, the clock can be placed on the D1 channel and a data lane can be used on the CLK

channel if this improves the layout. In addition, the signal lines of the TMUX646 are routed single ended on the

chip die. This makes the device suitable for differential and single-ended high-speed systems.

9.2.2.1 MIPI D-PHY Application

The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the

application. In addition, the signal lines of the TMUX646 are routed single ended on the chip die. This makes the

device suitable for differential and single-ended high-speed systems. This also allows the positive and negative

lines to be interchanged as necessary to facilitate the best layout possible for the application.

D-PHY application includes a differential clock and 4 differential data lanes. All the channels of the device

perform similar and the clock or data signals can be interchanged as necessary to facilitate the best layout

possible for the application.

www.ti.com

TMUX646

SCDS432 – JUNE 2021

Copyright © 2021 Texas Instruments Incorporated

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