DLPC4420ZPC datasheet(27/49 Pages) TI

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• The PLL feeding the LVDS DMD I/F (PLLD) defaults to its power-down mode and all derived clocks

are inactive with corresponding resets asserted (The ARM9 is responsible for enabling these clocks and

releasing associated resets).

• LVDS I/O defaults to its power-down mode with outputs tri-stated.

• All resets output by the DLPC4420 device remain asserted until released by the ARM9. (after boot-up)

• The ARM9 processor boots-up from external flash.

When the ARM9 boots-up, the ARM9 API:

• Configures the programmable DDR Clock Generator (DCG) clock rates (i.e. the DMD LVDS I/F rate)

• Enables the DCG PLL (PLLD) while holding divider logic in reset

• When the DCG PLL locks, ARM9 software sets DMD clock rates

• API software then releases DCG divider logic resets, which in turn, enable all derived DCG clocks

• Release external resets

Application software then typically waits for a wake-up command (through the soft power switch on the projector)

from the end user. When the projector is requested to wake-up, the software places the ASIC back in normal

mode, re-initialize clocks, and resets as required.

7.3.2 Spread Spectrum Clock Generator Support

The DLPC4420 controller supports limited, internally-controlled, spread spectrum clock spreading on the DMD

interface. The purpose of this is to frequency spread all signals on this high-speed, external interface to

reduce EMI emissions. Clock spreading is limited to triangular waveforms. The DLPC4420 controller provides

modulation options of 0%, +/-0.5% and +/-1.0% (center-spread modulation).

7.3.3 GPIO Interface

The DLPC4420 controller provides 83 software-programmable, general-purpose I/O pins. Each GPIO pin is

individually configurable as either input or output. In addition, each GPIO output can be either configured

as push-pull or open-drain. Some GPIO have one or more alternate-use modes, which are also software

configurable. The reset default for all GPIO is as an input signal. However, any alternate function connected

to these GPIO pins, with the exception of general purpose clocks and PWM generation, stay in reset. When

configured as open-drain, the outputs must be externally pulled-up (to the 3.3V supply). External pull-up or

pull-down resistors may be required to ensure stable operation before software is able to configure these ports.

7.3.4 Source Input Blanking

Vertical and horizontal blanking requirements for both input ports are defined as follows (See Video Timing

Parameter Definitions).

• Minimum port 1 and port 2 vertical blanking

– Vertical back porch (VBP): 370 µs

– Vertical front porch (VFP): 1 line

– Total vertical blanking (TVB): 370 µs + 2 lines

• Minimum port1 and port 2 horizontal blanking

– Horizontal back porch (HBP): 10 pixels

– Horizontal front porch (HFP): 0 pixels

– Total horizontal blanking (THB): 80 pixels

7.3.5 Video Graphics Processing Delay

The DLPC4420 controller introduces a variable number of field/ frame delays dependent on the source type and

selected processing steps performed on the source. For optimum audio/ video synchronization this delay must

be matched in the audio path. The following tables define various video delay scenarios to aid in audio matching.

Frame and Fields in table refer to source frames and fields.

• For 2-D sources, “N” is defined to be the ratio of the primary channel source frame rate (or field rate for

interlaced video) to the display frame/ field rate.

• For 3-D sources, “M” is defined to be the ratio of the primary channel source frame rate (or field rate for

interlaced video) required to obtain both the left and right image, to the display frame/field rate (The rate at

which each eye is displayed).

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DLPC4420

DLPS222 – DECEMBER 2021

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