DLPC4420ZPC datasheet(38/49 Pages) TI

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10.1.2 PCB Layout Guidelines for Auto-Lock Performance

One of the most important factors in getting good performance from Auto-Lock is to design the PCB with the

highest signal integrity possible by following the recommendations below:

• Place the ADC chip as close to the VESA/Video connectors as possible.

• Avoid crosstalk to the analog signals by keeping them away from digital signals

• Do not place the digital ground or power planes under the analog area between the VESA connector to the

ADC chip.

• Avoid crosstalk onto the RGB analog signals, by separating them from the VESA Hsync and Vsync signals.

• Analog power must not be shared with the digital power directly.

• Try to keep the trace lengths of the RGB as equal as possible.

• Use good quality (1%) termination resistors for the RGB inputs to the ADC

• If the green channel must be connected to more than the ADC green input and ADC sync-on-green input,

provide a good quality high impendence buffer to avoid adding noise to the green channel.

10.1.3 DMD Interface Considerations

High speed interface waveform quality and timing on the DLPC4420 controller (i.e. the LVDS DMD Interface)

is dependent on the total length of the interconnect system, the spacing between traces, the characteristic

impedance, etch losses, and how well matched the lengths are across the interface. Thus ensuring positive

timing margin requires attention to many factors.

As an example, DMD Interface system timing margin can be calculated as follows:

• Setup Margin = (DLPC4420 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI

degradation)

• Hold-time Margin = (DLPC4420 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI

degradation)

Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously

switching output (SSO) noise, cross-talk and inter-symbol interference (ISI) noise. The controller I/O timing

parameters as well as DMD I/O timing parameters can be easily found in their corresponding data sheets.

Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI

degradation is not so straight forward.

In an attempt to minimize the signal integrity analysis, the following PCB design guidelines are provided as a

reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for

both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but

have to be confirmed with PCB signal integrity analysis or lab measurements

PDB Design:

● Configuration

Asymmetric Dual Stripline

● Etch Thickness

1.0 oz copper (1.2 mil)

● Flex Etch Thickness

0.5 oz copper (0.6 mil)

● Single Ended Signal Impedance

50 ohms (+/- 10%)

● Differential Signal Impedance

100 ohms differential (+/- 10%)

PCB Stackup:

● Reference plane 1 is assumed to be a ground plane for proper return path

● Reference plane 2 is assumed to be the I/O power plane or ground

● Dielectric FR4, (Er):

4.2 (nominal)

● Signal trace distance to reference plane 1 (H1)

5.0 mil (nominal)

● Signal trace distance to reference plane 2 (H2)

34.2 mil (nominal)

DLPC4420

DLPS222 – DECEMBER 2021

www.ti.com

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