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ZL40272 Datasheet(PDF) 36 Page - Microchip Technology

Part # ZL40272
Description  Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control
PDF  54 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

ZL40272 Datasheet(HTML) 36 Page - Microchip Technology

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ZL40272
DS20006408B-page 36
2020 - 2021 Microchip Technology Inc. and its subsidiaries
Additive Jitter as per PCIe 3.0
(PLL_BW = 2 MHz to 5 MHz, CDR
= 10 MHz)
tjPCIe_3.0
—
24
30
fsRMS
Input clock:
100 MHz
Additive Jitter as per PCIe 4.0
(PLL_BW = 2 MHz to 5 MHz, CDR
= 10 MHz)
tjPCIe_4.0
—
24
30
fsRMS
Input clock:
100 MHz
Additive Jitter as per PCIe 5.0
(PLL_BW = 0.5 MHz to 1.8 MHz,
CDR for 32 GT/s CC)
tjPCIe_5.0
—
10
12
fsRMS
Input clock:
100 MHz
Additive Jitter as per Intel QPI
9.6 Gbps
tjQPI
—
45
55
fsRMS
Input clock:
100 MHz
Additive RMS Jitter in 1 MHz to
20 MHz Band
tj_1M_20M
—
64
75
fsRMS
Input clock:
100 MHz
—
48
60
Input clock:
133 MHz
—
26
33
Input clock:
400 MHz
Additive RMS Jitter in 12 kHz to
20 MHz Band
tj_12k_20M
—
68
83
fsRMS
Input clock:
100 MHz
—
52
66
Input clock:
133 MHz
—
31
43
Input clock:
400 MHz
Noise Floor
NF
—
–163
–161
dBc/Hz
Input clock:
100 MHz
—
–164
–162
Input clock:
133 MHz
—
–160
–158
Input clock:
400 MHz
Note 1: Values are over Recommended Operating Conditions.
TABLE 4-14: HCSL OUTPUTS (PCIe ELECTRICAL CHARACTERISTICS) FOR VDDO = 2.5V
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Rising Edge Rate
Rise_Rate
1.4
1.75
4
V/ns
Note 3, Note 4
Falling Edge Rate
Fall_Rate
1.4
1.75
4
V/ns
Note 3, Note 4
Differential High Voltage
VIH
0.6
—
—
V
Note 3
Differential Low Voltage
VIL
—
—
–0.6
V
Note 3
Single-Ended High Voltage
VSIH
0.65
0.75
0.85
V
DC Measurement
Single-Ended Low Voltage
VSIL
–20
0
20
mV
DC Measurement
Absolute Crossing Voltage
VCROSS
0.25
—
0.55
V
Note 2, Note 5,
Note 6
Variation of VCROSS over All Rising
Clock Edges
∆VCROSS
—
—
0.140
V
Note 2, Note 5,
Note 10
Ringback Voltage Margin
VRB
–0.55
—
0.55
V
Note 3, Note 12
Time before VRB is Allowed
tSTABLE
4.6
—
—
ns
Note 3, Note 12
Cycle-to-Cycle Additive Jitter
tJCC
—
4.6
5.8
psPP
Note 3
TABLE 4-13: HCSL (PCIe) JITTER PERFORMANCE FOR VDDO = 3.3V
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes



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