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STM32F732IE Datasheet(PDF) 165 Page - STMicroelectronics |
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STM32F732IE Datasheet(HTML) 165 Page - STMicroelectronics |
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165 / 226 page ![]() DS11854 Rev 6 165/226 STM32F732xx STM32F733xx Electrical characteristics 198 Figure 52. SPI timing diagram - slave mode and CPHA = 1 Figure 53. SPI timing diagram - master mode MSv41659V1 NSS input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output MOSI input tsu(SI) th(SI) tw(SCKL) tw(SCKH) tsu(NSS) tc(SCK) ta(SO) tv(SO) First bit OUT Next bits OUT Next bits IN Last bit OUT th(SO) tr(SCK) tf(SCK) th(NSS) tdis(SO) First bit IN Last bit IN ai14136c CPHA= 0 MOSI OUTPUT MISO INP UT CPHA= 0 LSB OUT LSB IN CPOL=0 CPOL=1 B I T1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) MSB IN BIT6 IN MSB OUT |
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