STM32F732IE datasheet(25/226 Pages) STMICROELECTRONICS

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DS11854 Rev 6

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STM32F732xx STM32F733xx

Functional overview

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HCLK/2 maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers.

It supports Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build

cost-effective graphic applications using LCD modules, with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

3.9

Quad-SPI memory interface (QUADSPI)

All the devices embed a Quad-SPI memory interface, which is a specialized communication

interface targeting single, dual or quad-SPI Flash memories. It can work in:

•

Direct mode through registers

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External Flash status register polling mode

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Memory-mapped mode

Up to 256 Mbytes of external Flash are memory mapped, supporting 8-, 16-, and 32-bit

access. The code execution is supported.

The opcode and the frame format are fully programmable. The communication can be either

in single-data rate or dual-data rate.

3.10

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 110 maskable interrupt channels, plus the 16 interrupt lines of the

Cortex-M7 with FPU core.

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Closely coupled NVIC gives low-latency interrupt processing

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Interrupt entry vector table address passed directly to the core

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Allows early processing of interrupts

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Processing of late arriving, higher-priority interrupts

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Support tail chaining

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Processor state automatically saved

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Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with a minimum

interrupt latency.

3.11

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs in the

STM32F732xx devices (138 GPIOs in the STM32F733xx devices) can be connected to the

16 external interrupt lines.

STM32F732IE Datasheet(PDF) 25 Page - STMicroelectronics

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