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STM32F732IE Datasheet(PDF) 24 Page - STMicroelectronics |
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STM32F732IE Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 226 page  Functional overview STM32F732xx STM32F733xx 24/226 DS11854 Rev 6 3.7 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with eight streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support a circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDMMC • ADC • SAI • QUADSPI 3.8 Flexible memory controller (FMC) The flexible memory controller (FMC) includes three memory controllers: • NOR/PSRAM memory controller • NAND/memory controller • synchronous DRAM (SDRAM/mobile LPSDR SDRAM) controller The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/oneNAND Flash memory – PSRAM (four memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data • Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories • 8-, 16-, 32-bit data bus width • Independent chip select control for each memory bank • Independent configuration for each memory bank • Write FIFO • Read FIFO for SDRAM controller |
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