STM32F732IE datasheet(26/226 Pages) STMICROELECTRONICS

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Functional overview

STM32F732xx STM32F733xx

26/226

DS11854 Rev 6

3.12

Clocks and startup

On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock.

The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application

can then select as system clock either the RC oscillator or an external 4-26 MHz clock

source. This clock can be monitored for failure. If a failure is detected, the system

automatically switches back to the internal RC oscillator and a software interrupt is

generated (if enabled). This clock source is input to a PLL thus allowing to increase the

frequency up to 216 MHz. Similarly, a full interrupt management of the PLL clock entry is

available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2), and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 216 MHz, while the maximum frequency of the high-speed APB domains is

108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.

The devices embed two dedicated PLLs (PLLI2S and PLLSAI) which allow audio class

performance to be achieved. In this case, the I2S and SAI master clock can generate all

standard sampling frequencies from 8 kHz to 192 kHz.

The STM32F733xx devices embed two PLLs inside the PHY HS controller: PLL1 and PLL2.

The PLL1 allows an output of 60 MHz used as an input for PLL2 which itself allows the

generation of 480 Mbps in the USB OTG High Speed mode.

The PLL1 has as input HSE clock.

3.13

Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option

bytes, allowing any boot memory address to be programmed from 0x0000 0000 to

0x3FFF FFFF, which includes:

•

all Flash address space mapped on ITCM or AXIM interface

•

all RAM address space: ITCM, DTCM RAMs, and SRAMs mapped on AXIM interface

•

system memory bootloader

The bootloader is located in system memory. It is used to reprogram the Flash memory

through a serial interface.

3.14

Power supply schemes

•

VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through VDD pins.

•

VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, reset blocks,

RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

•

VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Note:

The VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

Section 3.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode

versus device operating mode to identify the packages supporting this option.

•

The VDDSDMMC can be connected either to VDD or to an external independent power

supply (1.8 to 3.6 V) for the SDMMC2 pins (clock, command, and 4-bit data).

STM32F732IE Datasheet(PDF) 26 Page - STMicroelectronics

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