STM32WB55CC datasheet(54/193 Pages) STMICROELECTRONICS

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Functional overview

STM32WB55xx STM32WB35xx

54/193

DS11929 Rev 11

3.23

Universal synchronous/asynchronous receiver transmitter

(USART)

The devices embed one universal synchronous receiver transmitter.

This interface provides asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and has

LIN Master/Slave capability. It provides hardware management of the CTS and RTS signals,

and RS485 driver enable.

The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart

Card mode (ISO 7816 compliant) and SPI-like communication capability.

The USART supports synchronous operation (SPI mode), and can be used as an SPI

master.

The USART has a clock domain independent from the CPU clock, allowing it to wake up the

MCU from Stop mode using baudrates up to 200 kbaud. The wake up events from Stop

mode are programmable and can be:



the start bit detection



any received data frame



a specific programmed data frame.

The USART interface can be served by the DMA controller.

3.24

Low-power universal asynchronous receiver transmitter

(LPUART)

The device embeds one Low-Power UART, enabling asynchronous serial communication

with minimum power consumption. The LPUART supports half duplex single wire

communication and modem operations (CTS/RTS), allowing multiprocessor

communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the

system from Stop mode using baudrates up to 220 kbaud. The wake up events from Stop

mode are programmable and can be:



the start bit detection



any received data frame



a specific programmed data frame.

Only a 32.768 kHz clock (LSE) is needed for LPUART communication up to 9600 baud.

Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an

Independent clock

Wakeup from Stop 0 / Stop 1 mode on address match

Wakeup from Stop 2 mode on address match

1. X: supported

Table 14. I2C implementation (continued)

I2C features(1)

I2C1

I2C3

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