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STM32WB55 Datasheet(PDF) 158 Page - STMicroelectronics |
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STM32WB55 Datasheet(HTML) 158 Page - STMicroelectronics |
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158 / 193 page ![]() Electrical characteristics STM32WB55xx STM32WB35xx 158/193 DS11929 Rev 11 6.3.28 Clock recovery system (CRS) The devices embed a special block for the automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which can be derived from USB Sart Of Frame (SOF) signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 6.3.29 Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: Standard-mode (Sm): bit rate up to 100 kbit/s Fast-mode (Fm): bit rate up to 400 kbit/s Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (see the reference manual). Table 90. IWDG min/max timeout period at 32 kHz (LSI1)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit /4 0 0.125 512 ms /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 1. The exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC period of uncertainty. Table 91. Minimum I2CCLK frequency in all I2C modes Symbol Parameter Condition Min Unit f(I2CCLK) I2CCLK frequency Standard-mode - 2 MHz Fast-mode Analog filter ON, DNF = 0 9 Analog filter OFF, DNF = 1 9 Fast-mode Plus Analog filter ON, DNF = 0 19 Analog filter OFF, DNF = 1 16 |
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