PI3DPX1202A datasheet(23/51 Pages) DIODES

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February 2020

PI3DPX1202A

Document number: DS40115 Rev 3-3

PI3DPX1202A

4.5

DPCD Aux Registers

DPCD Aux Register Definitions

SMBus

Registers

AUX

Registers

Description

Default

value

DP Ac-

cess

0x02

Link initialization

field

AUX operation :

00100h

LINK_BW_SET : Main Link Bandwidth Setting=Value x 0.27Gbps per

lane

Bits 7:0 = LINK_BW_SET

For DisplayPort version 1, revision 1a, only three values are supported.

All other values are reserved.

06h = 1.62 Gbps per lane

0Ah = 2.7 Gbps per lane

14h = 5.4 Gbps per lane

The Source may choose any of the three link bandwidths as long as it

does not exceed the capability of DisplayPort receiver as indicated in the

receiver capability field.

14h

R/W

0x03

Link initialization

field

AUX operation :

00101h

LANE_COUNT_SET : Main Link Lane Count = Value

Bits 4:0 = LANE_COUNT_SET

For DisplayPort version 1 revision 1a, only the following three values are

supported. All other values are reserved.

1h = One lane

2h = Two lanes

4h = Four lanes

For one-lane configuration, Lane0 is used. For 2-lane configuration,

Lane0 and Lane1 are used. The source may choose any lane count as long

as it does not exceed the capability of the DisplayPort receiver as indi-

cated in the receiver capability field.

For DPCD Ver.1.0:

Bits 7:5 = RESERVED. Read all 0’s.

For DPCD Ver.1.1:

Bits 6:5 = RESERVED. Read all 0’s.

Bit 7 = ENHANCED_FRAME_EN

0 = Enhanced Framing symbol sequence is not enabled.

1 = Enhanced Framing symbol sequence for BS, SR, CPBS, and CPSR is

enabled. Applicable to SST mode only. A uPacket TX must set this bit to

1 when the uPacket RX has the ENHANCED_FRAME_CAP bit (Bit 7 of

DPCD 00002h) set to 1 (with the exception of eDP

operation).

04h

R/W

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