PI3DPX1202A datasheet(26/51 Pages) DIODES

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Diodes Incorporated

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February 2020

PI3DPX1202A

Document number: DS40115 Rev 3-3

PI3DPX1202A

SMBus

Registers

AUX

Registers

Description

Default

value

DP Ac-

cess

00207h

ADJUST_REQUEST_LANE2_3

(Bit definitions as in ADJUST_REQUEST_LANE0_1)

00h

0x0C

00218h

TEST_REQUEST: Test requested by the Sink Device. All other values

reserved.

Bit 0 = TEST_LINK_TRAINING

0 = no link training test requested

1 = link training test requested.

See TEST_LINK_RATE and TEST_LANE_COUNT for link rate and

linkwidth requested respectively.

Bit 1 = TEST_PATTERN

0 = no test pattern requested

1 = test pattern requested

Bit 2 = TEST_EDID_READ

0 = no EDID read test requested

1 = EDID read test requested.

00h

Checksum of the last EDID block read is written to TEST_EDID_

CHECKSUM. The source will also send a color square test pattern.

For DPCD version 1.0:

Bits 7:3 = RESERVED. Read all 0’s.

For DPCD version 1.1:

Bit 3 = PHY_TEST_PATTERN

Set = 1 to request the PHY test pattern as specified at address 00248h.

Bits 7:4 = Reserved. Read as zeros.

0x0D

00219h

TEST_LINK_RATE

Bits 7:0 = TEST_LINK_RATE

06h = 1.62 Gbps

0Ah = 2.7 Gbps

14h = 5.4 Gbps

00h

0x0E

00220h

TEST_LANE_COUNT

Bits 4:0 = TEST_LANE_COUNT

1h = one lane

2h = two lanes

4h = four lanes

All other values reserved.

Bits 7:5 = RESERVED. Read all 0’s.

00h

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