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SPC5643LFF2MLL6 Datasheet(PDF) 93 Page - NXP Semiconductors |
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SPC5643LFF2MLL6 Datasheet(HTML) 93 Page - NXP Semiconductors |
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93 / 136 page  Electrical characteristics MPC5643L Microcontroller Data Sheet, Rev. 10 NXP Semiconductors 93 tlpll DFMPLL lock time 6, 7 —— — 200 μs tdc D Duty cycle of reference —40 — 60 % CJITTER T CLKOUT period jitter8,9,10,11 Long-term jitter (avg. over 2 ms interval), fFMPLLOUT maximum –6 — 6 ns Δt PKJIT T Single period jitter (peak to peak) PHI @ 120 MHz, Input clock @ 4 MHz —— 175 ps PHI @ 100 MHz, Input clock @ 4 MHz —— 185 ps PHI @ 80 MHz, Input clock @ 4 MHz —— 200 ps Δt LTJIT T Long term jitter PHI @ 16 MHz, Input clock @ 4 MHz —— ±6 ns fLCK D Frequency LOCK range — –6 — 6 % fFMPLLOUT fUL D Frequency un-LOCK range — –18 — 18 % fFMPLLOUT fCS fDS D Modulation depth Center spread ±0.25 — ±2.0 % fFMPLLOUT Down spread –0.5 — -8.0 fMOD D Modulation frequency12 — — — 100 kHz 1 Considering operation with FMPLL not bypassed. 2 With FM; the value does not include a possible +2% modulation 3 “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked mode. 4 Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the fLOR window. 5 f VCO is the frequency at the output of the VCO; its range is 256–512 MHz. fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz. fSYS =fVCO÷ODF 6 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this FMPLL, load capacitors should not exceed these limits. 7 This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 8 This value is determined by the crystal manufacturer and board design. 9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f SYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 10 Proper PC board layout procedures must be followed to achieve specifications. 11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C JITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 12 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz. Table 23. FMPLL electrical characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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