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PPC5605BAMLL4R Datasheet(PDF) 38 Page - NXP Semiconductors

Part # PPC5605BAMLL4R
Description  MPC5607B Microcontroller Data Sheet
PDF  114 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PPC5605BAMLL4R Datasheet(HTML) 38 Page - NXP Semiconductors

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MPC5607B Microcontroller Data Sheet, Rev. 10
Electrical characteristics
NXP Semiconductors
38
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS)
—VSS − 0.1
—
V
Relative to VDD
—VDD +0.1
IINJPAD
SR Injected input current on any pin during
overload condition
—
−55
mA
IINJSUM
SR Absolute sum of all injected input currents
during overload condition
—
−50
50
TVDD
SR VDD slope to ensure correct power up
6
—3.07
0.25 V/µs
V/s
TA C-Grade Part
SR Ambient temperature under bias
fCPU
≤ 64 MHz8
−40
85
°C
TJ C-Grade Part
SR Junction temperature under bias
—
−40
110
TA V-Grade Part
SR Ambient temperature under bias
fCPU
≤ 64 MHz8
−40
105
TJ V-Grade Part
SR Junction temperature under bias
—
−40
130
TA M-Grade Part
SR Ambient temperature under bias
fCPU
≤ 64 MHz8
−40
125
TJ M-Grade Part
SR Junction temperature under bias
—
−40
150
1 100 nF capacitance needs to be provided between each V
DD/VSS pair.
2 330 nF capacitance needs to be provided between each V
DD_LV/VSS_LV supply pair.
3 470 nF capacitance needs to be provided between V
DD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal
to slope of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower.
4 100 nF capacitance needs to be provided between V
DD_ADC/VSS_ADC pair.
5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
6 Guaranteed by device validation
7 Minimum value of TV
DD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH)
8 When the FMPLL uses the frequency modulation with a modulation depth of 4% from the center spread frequency,
the maximum value of fCPU is 66.56 MHz.
Table 13. Recommended operating conditions (5.0 V)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD
1
SR Voltage on VDD_HV pins with respect to ground
(VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
VSS_LV
3
SR Voltage on VSS_LV (low voltage digital supply)
pins with respect to ground (VSS)
—VSS − 0.1 VSS +0.1
V
VDD_BV
4
SR Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
Relative to VDD
3.0
VDD +0.1
Table 12. Recommended operating conditions (3.3 V) (continued)
Symbol
Parameter
Conditions
Value
Unit
Min
Max



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