ADM3050EBRIZ datasheet(5/19 Pages) AD

5 / 19 page

Data Sheet

ADM3050E

Rev. B | Page 5 of 19

TIMING SPECIFICATIONS

All voltages are relative to their respective ground, 1.7 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise

noted. Typical specifications are at VDD1 = VDD2 = 5 V and TA = 25°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DRIVER

See Figure 2 and Figure 20,

tBIT_TXD = 200 ns, RL = 60 Ω,

CL = 100 pF

Maximum Data Rate

Mbps

Propagation Delay from TXD to Bus (Recessive to Dominant)

tTXD_DOM

Propagation Delay from TXD to Bus (Dominant to Recessive)

tTXD_REC

Transmit Dominant Timeout

tDT

1175

4000

µs

TXD low, see Figure 3

RECEIVER

See Figure 2 and Figure 22,

tBIT_TXD = 200 ns, RL = 60 Ω,

CL = 100 pF, CRXD = 15 pF

Falling Edge Loop Propagation Delay (TXD to RXD)

tLOOP_FALL

150

Rising Edge Loop Propagation Delay (TXD to RXD)

tLOOP_RISE

150

Loop Delay Symmetry (Minimum Recessive Bit Width)

tBIT_RXD

2 Mbps

450

550

tBIT_TXD = 500 ns

5 Mbps

160

220

tBIT_TXD = 200 ns

8 Mbps

140

tBIT_TXD = 125 ns

12 Mbps

91.6

tBIT_TXD = 83.3 ns

TIMING DIAGRAMS

TXD

0.3VDD1

0.7VDD1

0.5V

0.9V

VDD1

5 ×

tBIT_TXD

tTXD_REC

tTXD_DOM

tBIT_BUS

tBIT_RXD

tBIT_TXD

tLOOP_FALL

tLOOP_RISE

RXD

VOD/VID

0.7VDD1

Figure 2. Transceiver Timing Diagram

TXD

VOD

tDT

Figure 3. Dominant Timeout, tDT

ADM3050EBRIZ Datasheet(PDF) 5 Page - Analog Devices

ADM3050EBRIZ Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Datasheet Download

Link URL