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OM8373 Datasheet(PDF) 11 Page - NXP Semiconductors |
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OM8373 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 108 page  2004 Jan 15 11 Philips Semiconductors Tentative Device Specification TV signal processor-Closed Caption decoder with embedded µ-Controller OM8373; OM8378 A7H R/W P2CFGB Reserved Reserved Reserved Reserved Reserved Reserved Reserved P2CFGB<0> A8H R/W IE EA EBUSY ES2 ECC ET1 EX1 ET0 EX0 B0H R/W P3 Reserved Reserved Reserved Reserved P3<3> P3<2> P3<1> P3<0> B4H R/W TXT20 DRCS ENABLE OSD PLANES Reserved Reserved Reserved Reserved Reserved Reserved B5H R/W TXT21 DISP LINE<1> DISP LINES<0> CHAR SIZE<1> CHAR SIZE<0> Reserved CC ON I2C PORT EN Reserved B6H R TXT22 GPF1<7> GPF1<6> GPF1<5> GPF1<4> GPF1<3> GPF1<2> GPF1<1> GPF1<0> B7H R/W CCLIN 0 0 0 CS<4> CS<3> CS<2> CS<1> CS<0> B8H R/W IP 0 PBUSY PES2 PCC PT1 PX1 PT0 PX0 B9H R/W TXT17 0 FORCE ACQ<1> FORCE ACQ<0> FORCE DISP<1> FORCE DISP<0> Reserved Reserved Reserved BEH R/W P3CFGA Reserved Reserved Reserved Reserved P3CFGA<3> P3CFGA<2> P3CFGA<1> P3CFGA<0> BFH R/W P3CFGB Reserved Reserved Reserved Reserved P3CFGB<3> P3CFGB<2> P3CFGB<1> P3CFGB<0> C1H R/W TXT1 Reserved Reserved Reserved Reserved Reserved FIELD POLARITY Reserved Reserved C5H R/W TXT5 Reserved Reserved CORB OUT CORB IN Reserved Reserved Reserved Reserved C7H R/W TXT7 Reserved CURSOR ON Reserved Reserved Reserved Reserved Reserved Reserved C9H R/W TXT9 Reserved Reserved Reserved R<4> R<3> R<2> R<1> R<0> CAH R/W TXT10 CHAR 16/12 - C<5> C<4> C<3> C<2> C<1> C<0> CCH R TXT12 525/625 SYNC GPF2<4> GPF2<3> GPF2<2> GPF2<1> GPF2<0> 1 VIDEO SIGNAL QUALITY D0H R/W PSW C AC F0 RS1 RS0 OV - P D2H R/W TDACL TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0> D3H R/W TDACH TPWE 1 TD<13> TD<12> TD<11> TD<10> TD<9> TD<8> D5H R/W PWM0 PW0E 1 PW0V<5> PW0V<4> PW0V<3> PW0V<2> PW0V<1> PW0V<0> D6H R/W PWM1 PW1E 1 PW1V<5> PW1V<4> PW1V<3> PW1V<2> PW1V<1> PW1V<0> D7H R CCDAT1 CCD1<7> CCD1<6> CCD1<5> CCD1<4> CCD1<3> CCD1<2> CCD1<1> CCD1<0> D8H R/W S1CON CR<2> ENSI STA STO SI AA CR<1> CR<0> D9H R S1STA STAT<4> STAT<3> STAT<2> STAT<1> STAT<0> 0 0 0 DAH R/W S1DAT DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0> DBH R/W S1ADR ADR<6> ADR<5> ADR<4> ADR<3> ADR<2> ADR<1> ADR<0> GC DCH R/W PWM3 PW3E 1 PW3V<5> PW3V<4> PW3V<3> PW3V<2> PW3V<1> PW3V<0> E0H R/W ACC ACC<7> ACC<6> ACC<5> ACC<4> ACC<3> ACC<2> ACC<1> ACC<0> E4H R/W PWM2 PW2E 1 PW2V<5> PW2V<4> PW2V<3> PW2V<2> PW2V<1> PW2V<0> ADD R/W Names BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Table 1 SFR Map |
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