HT45R06 datasheet(14/41 Pages) HOLTEK

14 / 41 page

HT45R06

Rev. 1.00

May 24, 2005

Timer/Event Counter

A timer/event counter (TMR) is implemented in the

microcontroller. The timer/event counter contains an

8-bit programmable count-up counter and the clock may

come from an external source or the system clock.

Using external clock input allows the user to count exter-

nal events, measure time internals or pulse widths, or

generate an accurate time base. Using the internal clock

allows the user to generate an accurate time base.

The timer/event counter can generate a PFD signal by

using external or internal clock and PFD frequency is

determine by the equation fINT/[2

´(256-N)].

There are two registers related to the timer/event coun-

ter; TMR ([0DH]), TMRC ([0EH]). Two physical registers

are mapped to TMR location. Writing TMR makes the

starting value be placed in the timer/event counter

preload register and reading TMR retrieves the contents

of the timer/event counter. The TMRC is a timer/event

counter control register, which defines some options.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the fINT clock. The

pulse width measurement mode can be used to count

the high or low level duration of the external signal

(TMR). The counting is based on the fINT clock.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFH. Once over-

flow occurs, the counter is reloaded from the timer/event

counter preload register and generates the interrupt re-

quest flag (TF; bit 5 of the INTC) at the same time.

In the pulse width measurement mode with the TON and

TE bits equal to one, once the TMR has received a tran-

sient from low to high (or high to low if the TE bits is

²0²)

it will start counting until the TMR returns to the original

level and resets the TON. The measured result will re-

main in the timer/event counter even if the activated

transient occurs again. In other words, only one cycle

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transient pulse. Note that in this operating

mode, the timer/event counter starts counting not ac-

cording to the logic level but according to the transient

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and issues an interrupt request just like the other two

modes. To enable the counting operation, the timer ON

bit (TON; bit 4 of the TMRC) should be set to 1. In the

pulse width measurement mode, the TON will be

cleared automatically after the measurement cycle is

completed. But in the other two modes the TON can only

be reset by instructions. The timer/event counter over-

flow is one of the wake-up sources. No matter what the

operation mode is, writinga0toETIcan disable the in-

terrupt service.

Bit No.

Labels

Function

PSC0

PSC1

PSC2

Defines the prescaler stages, PSC2, PSC1, PSC0=

000: fINT=fSYS/1

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

3TE

Defines the TMR active edge of the timer/event counter:

In Event Counter Mode (TM1,TM0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (TM1,TM0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

TON

Enables or disables the timer counting

(0=disable; 1=enable)

Unused bit, read as

²0²

TM0

TM1

Defines the operating mode, TM1, TM0=

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMRC (0EH) Register

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