HT46R232 datasheet(10/50 Pages) HOLTEK

10 / 50 page

HT46R232/HT46C232

Rev. 1.40

November 23, 2005

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

External interrupts are triggered by a high to low transi-

tion of INT and the related interrupt request flag (EIF; bit

4 of INTC0) will be set. When the interrupt is enabled,

the stack is not full and the external interrupt is active, a

subroutine call to location 04H will occur. The interrupt

request flag (EIF) and EMI bits will be cleared to disable

other interrupts.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F; bit 5 of INTC0), which is normally

caused by a timer overflow. After the interrupt is en-

abled, and the stack is not full, and the T0F bit is set, a

subroutine call to location 08H occurs. The related inter-

rupt request flag (T0F) is reset, and the EMI bit is

cleared to disable further maskable interrupts. The

Timer/Event Counter 1 is operated in the same manner

but its related interrupt request flag is T1F (bit 6 of

INTC0) and its subroutine call location is 0CH.

The A/D converter interrupt is initialized by setting the

A/D converter request flag (ADF; bit 4 of INTC1),

caused by an end of A/D conversion. When the interrupt

is enabled, the stack is not full and the ADF is set, a sub-

routine call to location 10H will occur. The related inter-

rupt request flag (ADF) will be reset and the EMI bit

cleared to disable further interrupts.

The I

2C Bus interrupt is initialized by setting the I2C Bus in-

terrupt request flag (HIF; bit 5 of INTC1), caused by a

slave address match (HAAS=

²1²) or one byte of data

transfer is completed. When the interrupt is enabled, the

stack is not full and the HIF bit is set, a subroutine call to

location 14H will occur. The related interrupt request flag

(HIF) will be reset and the EMI bit cleared to disable further

interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the

²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (of course, if the stack is

not full). To return from the interrupt subroutine,

²RET² or

²RETI² may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Bit No.

Label

Function

EMI

Controls the master (global) interrupt (1= enabled; 0= disabled)

EEI

Controls the external interrupt (1= enabled; 0= disabled)

ET0I

Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)

ET1I

Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)

EIF

External interrupt request flag (1= active; 0= inactive)

T0F

Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)

T1F

Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)

For test mode used only.

Must be written as

²0²; otherwise may result in unpredictable operation.

INTC0 (0BH) Register

Bit No.

Label

Function

EADI

Control the A/D converter interrupt (1= enabled; 0=disabled)

EHI

Control the I

2C Bus interrupt (1= enabled; 0= disabled)

2, 3

Unused bit, read as

²0²

ADF

A/D converter request flag (1= active; 0= inactive)

HIF

2C Bus interrupt request flag (1= active; 0= inactive)

6, 7

Unused bit, read as

²0²

INTC1 (1EH) Register

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