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HT46R232 Datasheet(PDF) 14 Page - Holtek Semiconductor Inc |
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HT46R232 Datasheet(HTML) 14 Page - Holtek Semiconductor Inc |
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14 / 50 page  HT46R232/HT46C232 Rev. 1.40 14 November 23, 2005 The registers states are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Program Counter 000H 000H 000H 000H 000H TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PWM0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu INTC1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu HADR xxxx xxx- xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu- HCR 0--0 0--- 0--0 0--- 0--0 0--- 0--0 0--- u--u u--- HSR 100- -0-1 100- -0-1 100- -0-1 100- -0-1 uuuu uuuu HDR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL xx-- ---- xx-- ---- xx-- ---- xx-- ---- uu-- ---- ADRH xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu PF 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PFC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu Note: ²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown |
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