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L9963T Datasheet(PDF) 11 Page - STMicroelectronics

Part # L9963T
Description  Automotive general purpose SPI to isolated SPI transceiver
PDF  45 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9963T Datasheet(HTML) 11 Page - STMicroelectronics

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Figure 5. DIS pin structure
DIS
R
C
GND
f
CUT_DIG_IN
GND
V3V3_STBY
TO OPEN DRAIN OUTPUT
R
IN_PU
3.2.1.4
ISOFREQ
ISOFREQ pin is a digital input used to switch ISOline bit rate:
•
ISOFREQ = 1 selects fast operation: bit time is TBIT_LENGTH_FAST
•
ISOFREQ = 0 selects slow operation: bit time is TBIT_LENGTH_SLOW
ISOFREQ sampling depends on device state and configuration:
Table 9. ISOFREQ sampling strategy
L9963T
state
L9963T
configuration
ISOFREQ sampling
Note
Normal
state
Slave (NSLAVE =
0)
The ISOFREQ pin is latched upon NCS assertion. Therefore, it
must be stable at least TISOFREQ_DEGLITCH + TISOFREQ_SETUP
before NCS assertion. Moreover, ISOFREQ must be kept stable
TISOFREQ_HOLD after NCS assertion in order to fulfil hold time
constraints.
The new bit rate setting is immediately applied to the RX
interface, while it is applied to the TX interface after the SPI
frame has been completely transmitted over the isolated SPI
interface. This allows Managing ISOFREQ And TXAMP Pins
For Communicating With L9963
In case several SPI
frames are being pushed
into the TX queue, the
setting applied once the
TX interface is in idle
depends on the last one
latched (no pipelining
supported).
Master (NSLAVE =
1)
The ISOFREQ setting is simply resynchronized (TISOFREQ_SETUP
and TISOFREQ_HOLD requirements still apply) and deglitched
(TISOFREQ_DEGLITCH filter still present), but it is not latched upon
NCS assertion.
Stand-by
state
Slave/Master
(NSLAVE = X)
The new ISOFREQ setting is latched during the wake
up sequence. Hence, the ISOFREQ pin shall be stable
TISOFREQ_SETUP before the DIS high → low transition is applied
and shall not change during TWAKEUP.
-
Reset
state
Slave/Master
(NSLAVE = X)
The initial ISOFREQ setting is latched during the first power up
sequence. Hence, the ISOFREQ pin shall be stable before VDD
is applied and shall not change duringTFIRST_POWERUP.
-
The new bit rate of L9963T must be compatible with the one of all other units communicating on the same bus.
L9963T
Pin configuration
DS13590 - Rev 4
page 11/45



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