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L9963T Datasheet(PDF) 17 Page - STMicroelectronics |
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L9963T Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 45 page ![]() 3.2.1.8.2.2 Open drain (DIS) All parameters are tested and guaranteed in the following conditions, unless otherwise specified: 4.5 V ≤ VVDD ≤ 5.5 V ; -40 °C < Tj < 125 °C Table 13. Open drain electrical characteristics Symbol Parameters Test conditions Min Typ Max Unit VDISL - DIS output level when the pull down stage is ON IDIS = 5 mA - - 0.4 V IDIS_LIM - DIS output current limitation for VDIS = 5 V 8 - 18 mA TDIS_PULLDOWN Time interval after POR_MAIN when DIS pin is internally pulled-down, upon a wake up by VIF. Purpose is to trigger interrupt in the MCU or wake up on a PMIC. Guaranteed by SCAN - 800 - ms TDIS_DEGLITCH Up/Reset counter to avoid positive glitches on DIS input when the L9963T is in Normal state. The counter counts up if DIS = 1, while it is reset if DIS = 0. Guaranteed by SCAN 1 2 3 μs 3.2.2 Analog input 3.2.2.1 SPICLKFREQ SPICLKFREQ pin is an analog input, compared to four thresholds by a set of analog comparators. An external resistor RCLKPD must be connected between SPICLKFREQ and GND, in order to generate a voltage VSPICLKFREQ = RCLKPD * ISPICLKFREQPU. The code obtained from these 4 comparators outputs (as indicated in the following table) is latched in the Trimming & Config Latch to determine the SPI Clock frequency when L9963T works in Master mode (NSLAVE = 1). Figure 10. SPICLKFREQ thresholds Table 14. SPICLKFREQ thresholds VSPICLKFREQ [V] (typ.) Vcode [3:0] SCLK Frequency VSPICLKFREQ ≥ VCLKTH4 1111 250 kHz Circuit malfunction 1110 250 kHz 1101 250 kHz 1100 250 kHz 1011 250 kHz 1010 250 kHz 1001 250 kHz 1000 250 kHz VCLKTH3 ≤ VSPICLKFREQ < VCLKTH4 0111 8 MHz Circuit malfunction 0110 250 kHz 0101 250 kHz L9963T Pin configuration DS13590 - Rev 4 page 17/45 |
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