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TLC5940PWPR Datasheet(PDF) 7 Page - Texas Instruments

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Part # TLC5940PWPR
Description  16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
PDF  29 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLC5940PWPR Datasheet(HTML) 7 Page - Texas Instruments

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TLC5940
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTION
TERMINAL
NO.
I/O
DESCRIPTION
NAME
DIP
PWP
RHB
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also
BLANK
23
2
31
I
reset. When BLANK = L, OUTn are controlled by grayscale PWM control.
Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H,
DCPRG
19
26
25
I
DC is connected to the DC register.
DCPRG is also controls EEPROM writing, when VPRG = V(PRG)
GND
22
1
30
G
Ground
GSCLK
18
25
24
I
Reference clock for grayscale PWM control
IREF
20
27
26
I
Reference current terminal
12, 13,
NC
–
–
No connection
28, 29
OUT0
28
7
4
O
Constant current output
OUT1
1
8
5
O
Constant current output
OUT2
2
9
6
O
Constant current output
OUT3
3
10
7
O
Constant current output
OUT4
4
11
8
O
Constant current output
OUT5
5
12
9
O
Constant current output
OUT6
6
13
10
O
Constant current output
OUT7
7
14
11
O
Constant current output
OUT8
8
15
14
O
Constant current output
OUT9
9
16
15
O
Constant current output
OUT10
10
17
16
O
Constant current output
OUT11
11
18
17
O
Constant current output
OUT12
12
19
18
O
Constant current output
OUT13
13
20
19
O
Constant current output
OUT14
14
21
20
O
Constant current output
OUT15
15
22
21
O
Constant current output
SCLK
25
4
1
I
Serial data shift clock
SIN
26
5
2
I
Serial data input
SOUT
17
24
23
O
Serial data output
VCC
21
28
27
I
Power supply voltage
Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the
VPRG
27
6
3
I
device is in DC mode. When VPRG = V(PRG), DC register data can programmed into DC
EEPROM with DCPRG=HIGH.
XERR
16
23
22
O
Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.
Data latch. Note that the internal connections are switched by VPRG. At XLAT
↑ (VPRG =
XLAT
24
3
32
I
GND), GS register gets new data. At XLAT
↑ (VPRG = V
CC), DC register gets new data.
7



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