MPC8540 datasheet(239/1302 Pages) FREESCALE

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Memory Management

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-25

•

Supervisor mode page read access

•

Supervisor mode page write access

•

Write-through required (W)

•

Caching inhibited (I)

•

Memory coherence required (M) (ignored on the MPC8540)

•

Guarded (G)

•

Endianess (E)

•

User-definable (U0–U3), a 4-bit implementation-specific field

The core complex employs a two-level memory management unit (MMU) architecture. There are

separate instruction and data level-1 (L1) MMUs backed up by a unified level-2 (L2) MMU, as

shown in Figure 5-7.

Figure 5-7. MMU Structure

Level-1 MMUs have the following features:

•

Four-entry, fully associative TLB array that supports all nine page sizes

•

64-entry, 4-way set-associative TLB 4-Kbyte array that supports 4-Kbyte pages only

L2 MMUs

256-Entry

TLB Array

16-Entry

(TLB0)

TLB Array

(TLB1)

Unified

L1 Data MMU

64-Entry

D-L1TLB4K

4-Entry

D-L1VSP

L1 Instruction MMU

64-Entry

I-L1TLB4K

4-Entry

I-L1VSP

32-Kbyte I-Cache

Memory Unit

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