MPC8540 datasheet(236/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-22

Freescale Semiconductor

Core Complex Overview

Power PC architecture. They use save and restore registers (SRR0/SRR1) to save state

when they are taken and they use the rfi instruction to restore state. Asynchronous

noncritical interrupts can be masked by the external interrupt enable bit, MSR[EE].

3. Critical interrupts—Critical interrupts can be taken during a noncritical interrupt or during

regular program flow. They use the critical save and restore registers (CSRR0/CSRR1) to

save state when they are taken and they use the rfci instruction to restore state. These

interrupts can be masked by the critical enable bit, MSR[CE]. Book E defines the critical

input, watchdog timer, and machine check interrupts as critical interrupts, but the e500

defines a third set of resources for the machine check interrupt, as described in Table 5-6.

All interrupts except machine check are ordered within the two categories of noncritical and

critical, such that only one interrupt of each category is reported, and when it is processed (taken),

no program state is lost. Because save/restore register pairs are serially reusable, program state

may be lost when an unordered interrupt is taken.

5.8.4

Upper Bound on Interrupt Latencies

Core complex interrupt latency is defined as the number of core clocks between the sampling of

the interrupt signal as asserted and the initiation of the IVOR fetch (that is, the fetch of the first

instruction in the handler). Core complex interrupt latency is determinate unless a guarded load or

a cache-inhibited stwcx. is being executed, in which case the latency is indeterminate. The

minimum latency is 3 core clocks and the maximum is 8, not including the 2 bus clock cycles

required to synchronize the interrupt signal from the pad.

When an interrupt is taken, all instructions in the IQ are thrown away except if the oldest

instruction is a load/store instruction. That is, if an asynchronous interrupt is being serviced and

the oldest instruction is not a load/store instruction, the core complex goes straight from sampling

the interrupt to ensuring a recoverable state and issuing an exception. If a load/store instruction is

oldest, the core complex waits 4 clocks before ensuring a recoverable state. During this time, any

instruction finished by the LSU is deallocated.

5.8.5

Interrupt Registers

The registers associated with interrupt and exception handling are described in Table 5-6.

Table 5-6. Interrupt Registers

Description

Noncritical Interrupt Registers

SRR0

Save/restore register 0—Holds the address of the instruction causing the exception or the address of the

instruction that will execute after the rfi instruction.

SRR1

Save/restore register 1—Holds machine state on noncritical interrupts and restores machine state after an

rfi instruction is executed.

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