MPC8540 datasheet(234/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-20

Freescale Semiconductor

Core Complex Overview

5.7

On-Chip Cache Implementation

The core complex contains separate 32-Kbyte, eight-way set-associative, level 1 (L1) instruction

and data caches to give rapid access to instructions and data.

The data cache supports four-state MESI memory coherency protocol with 3-bit status and 1-bit

coherency valid fields. The core complex broadcasts all cache management functions based on the

setting of the address broadcast enable bit, HID1[ABE], allowing management of other caches in

the system.

On the MPC8540 the ABE bit must be set to ensure that cache and TLB management instructions

operate properly on the L2 cache.

The caches implement a pseudo-least-recently-used (PLRU) replacement algorithm.

Parity generation and checking may be enabled for both caches, and each cache can be

independently invalidated through L1CSR1 and L1CSR0. Additionally, instructions are provided

to perform cache locking and unlocking on both data and instruction caches on a cache-block

granularity. These are listed in Section 5.10.3, “Cache Control Instructions.”

Individual instruction cache lines and data cache lines can be invalidated using the icbi and dcbi

instructions, respectively. The entire data cache can be invalidated by setting L1CSR0[CFI]; the

entire instruction cache can be invalidated by setting L1CSR1[ICFI].

5.8

Interrupts and Exception Handling

The e500 core supports an extended exception handling model, with nested interrupt capability

and extensive interrupt vector programmability. The following sections define the exception

model, including an overview of exception handling as implemented on the e500 core, a brief

description of the exception classes, and an overview of the registers involved in the processes.

5.8.1

Exception Handling

In general, interrupt processing begins with an exception that occurs due to external conditions,

errors, or program execution problems. When the exception occurs, the processor checks to verify

interrupt processing is enabled for that particular exception. If enabled, the interrupt causes the

state of the processor to be saved in the appropriate registers, and prepares to begin execution of

the handler located at the associated vector address for that particular exception.

Once the handler is executing, the implementation may need to check one or more bits in the

exception syndrome register (ESR) or the SPEFSCR, depending on the exception, to verify the

specific cause of the exception and take appropriate action.

The core complex provides the interrupts described in Section 5.8.5, “Interrupt Registers.”

MPC8540 Datasheet(PDF) 234 Page - Freescale Semiconductor, Inc