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MPC8540 Datasheet(PDF) 233 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 233 Page - Freescale Semiconductor, Inc |
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233 / 1302 page  Programming Model MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 5-19 Figure 5-6. e500 Core Programming Model User-Level Registers General-Purpose Registers Instruction-Accessible Registers User General SPR (Read/Write) 0 31 32 63 0 31 32 63 32 63 User SPR general 01 1 USPRG0 is a separate physical register from SPRG0. (upper) GPR02 (lower) 2 The 64-bit GPR registers are accessed by the SPE as separate 32-bit registers by SPE instructions. Only SPE vector instructions can access the upper word. General- purpose registers CR Condition register spr 256 USPRG0 GPR1 spr 9 CTR Count register General SPRs (Read-Only) GPR2 spr 8 LR Link register spr 259 SPRG3 SPR general registers 3–7 GPR31 spr 260 SPRG4 spr 1 XER Integer exception register • • • Performance Monitor Registers (Read-Only PMRs) spr 512 SPEFSCR3 3 These registers are defined by the EIS and are not part of the Book E architecture. SPE FP status/control register spr 263 SPRG7 ACC 3 Accumulator Time-Base Registers (Read-Only) Global control register pmr 384 UPMGC0 3 Miscellaneous Registers spr 268 TBL Time base lower/upper pmr 0–3 UPMCs 3 Counter registers 0–3 spr 269 TBU spr 513 BBEAR 3 Branch buffer entry address register pmr 128–131 UPMLCas 3 Local control registers a0–a3 L1 Cache (read-only) spr 514 BBTAR 3 Branch buffer target address register L1 cache configuration registers 0–1 pmr 256–259 UPMLCbs 3 Local control registers b0–b3 spr 515 L1CFG0 3 spr 516 L1CFG1 3 Supervisor-Level Registers Interrupt Registers Configuration Registers 32 63 32 63 32 63 spr 63 IVPR Interrupt vector prefix spr 400 IVOR0 Interrupt vector offset registers 0–15 MSR Machine state spr 401 IVOR1 spr 26 SRR0 Save/restore registers 0/1 spr 1023 SCR System version • • • spr 27 SRR1 spr 415 IVOR15 spr 286 PIR Processor ID spr 58 CSRR0 Critical SRR 0/1 Processor version spr 528 IVOR32 3 Interrupt vector offset registers 32–35 spr 287 PVR spr 59 CSRR1 spr 529 IVOR33 3 Timer/Decrementer Registers spr 570 MCSRR0 3 Machine check SRR 0/1 spr 530 IVOR34 3 spr 571 MCSRR1 3 spr 531 IVOR35 3 spr 22 DEC Decrementer Exception syndrome register spr 62 ESR MMU Control and Status (Read/Write) Decrementer auto-reload spr 54 DECAR MMU control and status register 0 spr 572 MCSR 3 Machine check syndrome register spr 1012 MMUCSR0 3 spr 284 TBL Time base lower/upper spr 573 MCAR Machine check address register spr 624 MAS0 3 MMU assist registers 0–4 and 6 spr 285 TBU spr 625 MAS1 3 spr 61 DEAR Data exception address register spr 340 TCR Timer control spr 626 MAS2 3 spr 627 MAS3 3 spr 336 TSR Timer status Debug Registers spr 628 MAS4 3 Miscellaneous Registers spr 308 DBCR0 Debug control registers 0–2 spr 630 MAS6 3 spr 309 DBCR1 spr 1008 HID0 3 Hardware implementation dependent 0–1 spr 48 PID0 Process ID registers 0–2 spr 310 DBCR2 spr 1009 HID1 3 spr 633 PID1 3 spr 304 DBSR Debug status register spr 634 PID2 3 spr 1013 BUCSR4 4 These registers are e500-specific. Branch control and status register spr 312 IAC1 Instruction address compare registers 1–4 MMU Control and Status (Read Only) spr 272–279 SPRG0–7 General SPRs 0–7 spr 313 IAC2 spr 1015 MMUCFG 3 MMU configuration Performance Monitor Registers Data address compare registers 1 and 2 spr 316 DAC1 spr 688 TLB0CFG 3 TLB configuration 0/1 pmr 400 PMGC0 3 Global control spr 317 DAC2 spr 689 TLB1CFG 3 pmr 16–19 PMC0–3 3 Counter registers 0–3 spr 318 DVC1 Data value compare registers 1 and 2 L1 Cache (Read/Write) spr 319 DVC2 pmr 144–147 PMCa0–3 3 Local control a0–a3 spr 1010 L1CSR0 3 L1 cache control/ status 0/1 pmr 272–275 PMCb0–3 3 Local control b0–b3 spr 1011 L1CSR1 3 |
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