MPC8540 datasheet(229/1302 Pages) FREESCALE

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Instruction Flow

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-15

If a branch resolves as correct, instructions in the target stream are marked nonspeculative and are

allowed to complete. If the branch history bits in the BTB indicated weakly taken or weakly not

taken, the prediction is upgraded to strongly taken or strongly not taken.

If a branch resolves as incorrect, instructions in the target stream are flushed from the execution

pipeline, the branch history bits are updated in the BTB entry, and nonspeculative fetching begins

from the correct path.

5.5.3

e500 Execution Pipeline

The seven stages of the e500 execution pipeline—fetch1, fetch2/predecode, decode/dispatch,

issue, execute, complete, and write back—are highlighted in grey in Figure 5-4.

Figure 5-4. Instruction Pipeline Flow

Decode Stage

SU1

Maximum four-instruction

SU2

fetch per clock cycle

Fetch Stage 1

Fetch Stage 2

Completion Stage

Write-Back Stage

General Issue Queue (GIQ)

Execute Stage

Maximum two-instruction

completion per clock cycle

LSU Stage 1

Stage 2

Stage 3

MU Stage 1

Stage 2

Stage 3

Stage 4

At dispatch, instructions are deallocated from the

IQ and assigned sequential positions in the CQ.

Instruction Cache

Maximum two-instruction per cycle dispatch

to the issue queues. BIQ can accept one

per cycle; GIQ can accept at most two.

Issue Stage

Divide Bypass

Postdivide

Divide

Execute

Finish

Indicates stages

Branch Issue Queue (BIQ)

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