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MPC8540 Datasheet(PDF) 225 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 225 Page - Freescale Semiconductor, Inc |
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225 / 1302 page ![]() Features MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 5-11 — Low-power, 1.5-V design — Internal clock multipliers ranging from 1 to 8 times the bus clock, including integer and half-mode multipliers. The MPC8540 supports multipliers of 2, 2.5, 3, and 3.5. — Power-saving modes: core-halted and core-stopped — Dynamic power management of execution units, caches, and MMUs — NAP, DOZE, and SLEEP bits in HID0 can be used to assert nap, doze, and sleep output signals to initiate power-saving modes at the integrated device level. • Testability — LSSD scan design — JTAG interface — ESP support — ABIST for arrays —LBIST • Reliability and serviceability — Parity checking on caches — Parity checking on e500 local bus |
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