MPC8540 datasheet(222/1302 Pages) FREESCALE

Part #	MPC8540

Description	MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual

PDF	1302 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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222 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-8

Freescale Semiconductor

Core Complex Overview

Figure 5-2. Four-Stage MU Pipeline, Showing Divide Bypass

The MU has the following features:

— Four-cycle latency for all multiplication, including SPE integer and fractional multiply

instructions and embedded scalar and vector floating-point multiply instructions

— Variable-latency divide: 4, 11, 19, and 35 cycles for all integer divide instructions. If rA

or rB is zero, floating-point divide instructions take 4 cycles. All others take 29. Note

that although most divide instructions take more than 4 cycles to execute, the MU

allows subsequent multiply instructions to execute through all four MU stages in

parallel with the divide.

— Four-cycle floating-point add and subtract

•

Load/store unit (LSU) is shown in Figure 5-3.

Upper

Lower

MU-3

MU-1

MU-2

Divide Bypass Path

Postdivide

Divide

Reservation

Station

From GIQ0 or GIQ1

MU-4

MPC8540 Datasheet(PDF) 222 Page - Freescale Semiconductor, Inc