MPC8540 datasheet(218/1302 Pages) FREESCALE

218 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-4

Freescale Semiconductor

Core Complex Overview

The processor core integrates two simple instruction units (SU1, SU2), a multiple-cycle

instruction unit (MU), a branch unit (BU), and a load/store unit (LSU).

The LSU and SU2 support 64- and 32-bit instructions.

The ability to execute five instructions in parallel and the use of simple instructions with short

execution times yield high efficiency and throughput. Most integer instructions execute in one

clock cycle. A series of independent vector floating-point add instructions can be issued and

completed with a throughput of one instruction per cycle.

The core complex includes independent, on-chip, 32-Kbyte, eight-way set-associative, physically

addressed caches for instructions and data. It also includes on-chip first-level instruction and data

memory management units (MMUs) and an on-chip second-level unified MMU.

•

The first-level MMUs contain two four-entry, fully-associative instruction and data

translation lookaside buffer (TLB) arrays that provide support for demand-paged virtual

memory address translation and variable-sized pages. They also contain two 64-entry,

four-way set-associative instruction and data TLB arrays that support 4-Kbyte pages. These

arrays are maintained completely by the hardware with a true least-recently-used (LRU)

algorithm.

•

The second-level MMU contains a 16-entry, fully-associative unified (instruction and data)

TLB array that provides support for variable-sized pages and a 256-entry, two-way

set-associative unified TLB for 4-Kbyte page size support. These TLBs are maintained

completely by the software.

The core complex allows cache-line-based user-mode locks on the contents in either the

instruction or data cache. This provides embedded applications with the capability for locking

interrupt routines or other important (time-sensitive) instruction sequences into the instruction

cache. It also allows data to be locked into the data cache, which supports deterministic execution

time.

The core complex supports a high-speed on-chip internal bus with data tagging called the core

complex bus (CCB). The CCB has two general purpose read data buses, one write data bus, data

parity bits, data tag bits, an address bus, and address attribute bits. The processor core complex

supports out-of-order reads, in-order writes, and one level of pipelining for addresses with

address-retry responses. It can also support single-beat and burst data transfers for memory

accesses and memory-mapped I/O operations.

5.2

e500 Processor and System Version Numbers

Table 5-1 matches the revision code in the processor version register (PVR) and the system version

through the e500 core (see Chapter 6, “Core Register Summary”) or as memory-mapped registers

defined by the integrated device (see Section 18.4.1, “Register Descriptions”).

MPC8540 Datasheet(PDF) 218 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 218 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL