MPC8540 datasheet(219/1302 Pages) FREESCALE

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Features

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-5

5.3

Features

Key features of the e500 are summarized as follows:

•

Implements Book E 32-bit architecture

•

Auxiliary processing units

The branch target buffer (BTB) locking APU is specific to the e500. The BTB locking APU

gives the user the ability to lock, unlock, and invalidate BTB entries. The EIS defines the

following APUs:

— Integer select. This APU consists of the Integer Select instruction, isel, which is a

conditional register move that helps eliminate conditional branches, decreases latency,

and reduces the code footprint.

— Performance monitor. The performance monitor facility provides the ability to monitor

and count predefined events such as processor clocks, misses in the instruction cache or

data cache, types of instructions decoded, or mispredicted branches. The count of such

events can be used to trigger the performance monitor exception. Additional

performance monitor registers (PMRs) similar to SPRs are used to configure and track

performance monitor operations. These registers are accessed with the Move to PMR

and Move from PMR instructions (mtpmr and mfpmr). See Section 5.12,

“Performance Monitoring.”

— Cache line lock and unlock. This APU allows instructions and data to be locked into

their respective caches on a cache line basis. Locking is performed by a set of

touch-and-lock set instructions. This functionality can be enabled for user mode by

setting MSR[UCLE]. The APU also provides resources for detecting and handling

overlocking conditions.

— Machine check. The machine check interrupt is treated as a separate level of interrupt.

It uses its own save and restore registers (MCSRR0 and MCSRR1) and Return from

Machine Check Interrupt (rfmci) instruction. See Section 5.8, “Interrupts and

Exception Handling.”

— Single-precision embedded scalar and vector floating-point APUs. These instructions

are listed in the EREF: A Reference for Freescale Semiconductor Book E and the e500

Core.

Table 5-1. Revision Level-to-Device Marking Cross-Reference

MPC8540

Revision

e500 Core

Revision

Processor Version Register

(PVR)

System Version Register

(SVR)

1.0

0x8020_0010

0x8030_0010

2.0

0x8021_0010

0x8030_0020

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