MPC8540 datasheet(224/1302 Pages) FREESCALE

224 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-10

Freescale Semiconductor

Core Complex Overview

•

Extended exception handling

— Supports Book E interrupt model

– Less than 10-cycle interrupt latency

– Interrupt vector prefix register (IVPR)

– Vector offset registers (IVORs) 0–15 as defined in Book E, plus e500-defined IVORs

32–35

– Exception syndrome register (ESR)

– Book E-defined preempting critical interrupt, including critical interrupt status

registers (CSRR0 and CSRR1) and an rfci instruction

— e500-specific interrupts not defined in Book E architecture

– Machine-check APU

– SPE APU unavailable exception

– Floating-point data exception

– Floating-point round exception

– Performance monitor

•

Memory management unit (MMU)

— 32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual

address)

— TLB entries for variable (4-Kbyte–256-Mbyte) and fixed-size (4-Kbyte) pages

— Data L1 MMU

– 4-entry, fully associative TLB array for variable-sized pages

– 64-entry, 4-way set-associative TLB for 4-Kbyte pages

— Instruction L1 MMU

– 4-entry, fully associative TLB array for variable-sized pages

– 64-entry, 4-way set-associative TLB for 4-Kbyte pages

— Unified L2 MMU

– 16-entry, fully associative TLB array for variable-sized pages

– A 256-entry, 2-way set-associative unified (for instruction and data accesses) L2

TLB array (TLB0) supports only 4-Kbyte pages

— Software reload for TLBs

— Virtual memory support for as much as 4 Gbytes (232) of effective address space

— Real memory support for as much as 4 Gbytes (2

32) of physical memory

— Support for big-endian and true little-endian memory on a per-page basis

•

Power management

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