MPC8540 datasheet(226/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-12

Freescale Semiconductor

Core Complex Overview

5.4

Instruction Set

The e500 implements the following instructions:

•

The Book E instruction set for 32-bit implementations. This is composed primarily of the

user-level instructions defined by the PowerPC user instruction set architecture (UISA).

The e500 does not include Book E floating-point, load string, or store string instructions.

•

The e500 supports the following implementation-specific instructions:

— Integer select APU. This APU consists of the Integer Select instruction (isel), which

functions as an if

-then-else statement that selects between two source registers by

comparison to a CR bit. This instruction eliminates conditional branches, decreases

band latency, and reduces the code footprint.

— Performance monitor APU. Table 5-2 lists performance monitor APU instructions.

— Cache line lock and unlock APU. The cache block lock and unlock APU consists of the

instructions described in Table 5-3.

— Machine check APU. This APU defines the Return from Machine Check Interrupt

instruction (rfmci).

— SPE APU vector instructions. New vector instructions are defined that view the 64-bit

GPRs as being composed of a vector of two 32-bit elements (some of the instructions

also read or write 16-bit elements). Some scalar instructions are defined for DSP that

produce a 64-bit scalar result.

— The embedded floating-point APUs provide single-precision scalar and vector

floating-point instructions. Scalar floating-point instructions use only the lower 32 bits

of the GPRs for single-precision floating-point calculations. Table 5-4 lists embedded

floating-point instructions.

Table 5-2. Performance Monitor APU Instructions

Name

Mnemonic

Syntax

Move from Performance Monitor Register

mfpmr

rD,PMRN

Move to Performance Monitor Register

mtpmr

PMRN,rS

Table 5-3. Cache Block Lock and Unlock APU Instructions

Name

Mnemonic

Syntax

Data Cache Block Lock Clear

dcblc

CT, rA, rB

Data Cache Block Touch and Lock Set

dcbtls

CT, rA, rB

Data Cache Block Touch for Store and Lock Set

dcbtstls

CT, rA, rB

Instruction Cache Block Lock Clear

icblc

CT, rA, rB

Instruction Cache Block Touch and Lock Set

icbtls

CT, rA, rB

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