MPC8540 datasheet(230/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-16

Freescale Semiconductor

Core Complex Overview

The common pipeline stages are as follows:

•

Instruction fetch—Includes the clock cycles necessary to request an instruction and the time

the memory system takes to respond to the request. Instructions retrieved are latched into the

instruction queue (IQ) for subsequent consideration by the dispatcher.

Instruction fetch timing depends on many variables, such as whether an instruction is in the

on-chip instruction cache or an L2 cache (if implemented). Those factors increase when it

is necessary to fetch instructions from system memory and include the processor-to-bus

clock ratio, the amount of bus traffic, and whether any cache coherency operations are

required.

Because there are so many variables, unless otherwise specified, the instruction timing

examples in this chapter assume optimal performance and show the portion of the fetch

stage in which the instruction is in the instruction queue. The fetch1 and fetch2 stages are

primarily involved in retrieving instructions.

•

The decode/dispatch stage fully decodes each instruction; most instructions are dispatched

to the issue queues (however, isync, rfi, sc, nops, and some other instructions do not go to

issue queues).

•

The two issue queues, BIQ and GIQ, can accept as many as one and two instructions,

respectively, in a cycle. The behavior of instruction dispatch is covered in significant detail

in the e500 Software Optimization Guide. The following is a simplification that covers most

cases:

— Instructions dispatch only from the two lowest IQ entries—IQ0 and IQ1.

— A total of two instructions can be dispatched to the issue queues per clock cycle.

— Space must be available in the CQ for an instruction to decode and dispatch (this includes

instructions that are assigned a space in the CQ but not in an issue queue).

Dispatch is treated as an event at the end of the decode stage. The issue stage reads source

operands from rename registers and register files and determines when instructions are

latched into the execution unit reservation stations. Note that the e500 has 14 rename

registers, one for each completion queue entry, so instructions cannot stall because of a

shortage of rename registers.

The general behavior of the two issue queues is described as follows:

— The GIQ accepts as many as two instructions from the dispatch unit per cycle. SU1,

SU2, MU, and all LSU instructions (including 64-bit loads and stores) are dispatched to

the GIQ, shown in Figure 5-5.

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