MPC8540 datasheet(231/1302 Pages) FREESCALE

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Instruction Flow

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-17

Figure 5-5. GPR Issue Queue (GIQ)

Instructions can be issued out-of-order from the bottom two GIQ entries (GIQ1–GIQ0).

GIQ0 can issue to SU1, MU, and LSU. GIQ1 can issue to SU2, MU, and LSU.

Note that SU2 executes a subset of the instructions that can be executed in SU1. The

ability to identify and dispatch instructions to SU2 increases the availability of SU1 to

execute more computational-intensive instructions.

An instruction in GIQ1 destined for SU2 or the LSU need not wait for an MU

instruction in GIQ0 that is stalled behind a long-latency divide.

•

The execute stage accepts instructions from its issue queue when the appropriate

reservation stations are not busy. In this stage, the operands assigned to the execution stage

from the issue stage are latched.

The execution unit executes the instruction (perhaps over multiple cycles), writes results on

its result bus, and notifies the CQ when the instruction finishes. The execution unit reports

any exceptions to the completion stage. Instruction-generated exceptions are not taken until

the excepting instruction is next to retire.

Most integer instructions have a 1-cycle latency, so results of these instructions are

available 1 clock cycle after an instruction enters the execution unit. The MU and LSU are

pipelined, as shown in Figure 5-4.

Branches resolve in execute stage. If a branch is mispredicted, it takes 5 cycles for the next

instruction to reach the execute stage.

•

The complete and write-back stages maintain the correct architectural machine state and

commit results to the architecture-defined registers in the proper order. If completion logic

detects an instruction containing an exception status or a mispredicted branch, all following

instructions are cancelled, their execution results in rename registers are discarded, and the

correct instruction stream is fetched.

The complete stage ends when the instruction is retired. Two instructions can be retired per

clock cycle. If no dependencies exist, as many as two instructions are retired in program

order.

The write-back stage occurs in the clock cycle after the instruction is retired.

The e500 core also provides new instructions that perform single-instruction, multiple-data

(SIMD) operations. These signal processing instructions consist of parallel operations on both the

GIQ1

GIQ3

GIQ0

GIQ2

To SU2, MU, or LSU

From IQ0/IQ1

To SU1, MU, or LSU

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