MPC8540 datasheet(248/1302 Pages) FREESCALE

248 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-34

Freescale Semiconductor

Core Complex Overview

HID0

implementation

SEL_TBCLK bit. Selects time base clock. If this bit is set and the time base is enabled, the time base is based

on the TBCLK input, which on the PowerQUICC III devices is RTC.

HID1

Implementation

PLL_MODE Set to 01

PLL_CFG. PowerQUICC III devices support the following:

00010 0 2:1

00010 1 5:2 (2.5:1)

00011 0 3:1

00011 1 7:2 (3.5:1)

NEXEN, R1DPE, R2DPE, MPXTT, MSHARS, SSHAR, ATS, and MID are not implemented

On PowerQUICC III devices, ABE must be set to ensure that cache and TLB management instructions

operate properly on the L2 cache.

HID1[RFXE] controls whether assertion of core_fault_in causes a machine check interrupt. Assertion of

core_fault_in can result from uncorrectable data error, such as an L2 multibit ECC error. It can also occur for

a system error if logic on the integrated device signals a fault for nonfatal errors (read data is corrupt (or zero),

but the transaction can complete without corrupting other system state, making it unnecessary to take a

machine check (for example, a master abort of a PCI transaction).

If RFXE is 0, and core_fault_in is asserted, any data on the CCB is dropped, either stalling the load/store unit

and causing the e500 pipeline to stall until an interrupt occurs (typically generated by the programmable

interrupt controller (PIC) in response to the fault) or allowing processingþto continue with the bad data until

the interrupt occurs. Because core_fault_in cannot cause a machine check if RFXE is 0, it is critical that the

system be configured to generate the appropriate interrupt, as described below.

It is also possible to hang the processor (requiring a hard reset to recover) if a guardedþload hits in the L2

cache and gets an uncorrectable ECC error. Because of this, avoid defining memory as cacheable but

guarded. If this combination is required, RFXE must be enabled, in which case an error causes both a

machine check interrupt and an external interrupt when a bus fault condition is detected unless interrupts are

masked for all sources of bus faults.

If RFXE is 0, conditions that cause the assertion of core_fault_in cannot directly cause the e500 to generate

a machine check; however, PowerQUICC III devices must be configured to detect and enable such

conditions. The following describes how error bits should be configured:

• ECM mapping errors: EEER[LAEE] must be set. See Section 8.2.1.4, “ECM Error Enable Register

(EEER).”

• L2 multiple-bit ECC errors: L2ERRDIS[MBECCDIS] must be cleared to ensure that error can be detected.

L2ERRINTEN[MBECCINTEN] must be set. SeeSection 7.3.1.5, “L2 Error Registers.”

• DDR multiple-bit ECC errors. ERR_DISABLE[MBED] and ERR_INT_EN[MBEE] must be zero and

DDR_SDRAM_CFG[ECC_EN] must be one to ensure that an interrupt is generated. See Section 9.4.1,

“Register Descriptions.”

• PCI. The appropriate parity detect and master-abort bits in ERR_DR must be cleared and the

corresponding enable bits in ERR_EN must be set to ensure that an interrupt is generated.

Section 16.3.1.4, “PCI/X Error Management Registers.”

• Local bus controller parity errors. LTEDR[PARD] must be cleared and LTEIR[PARI] must be set to ensure

that an parity errors can generate an interrupt. See Section 13.3.1.11, “Transfer Error Check Disable

• RapidIO. PCR[CCE] must be set to ensure that an interrupt is generated due to a CRC error. See

Section 17.3.2.1.2, “Port Configuration Register (PCR).”

RFXE must also be set if software requires that code execution stop immediately when a bus fault occurs

rather than continuing with the bad data until the interrupt arrives. Again, this results in both a machine check

interrupt and an external interrupt when a bus fault is detected, unless all possible sources for bus fault have

their interrupts masked.þThe machine check interrupt can then reenable normal interrupts and wait for the

interrupt due to the fault to be received before returning from the machine check.

Table 5-8. Differences Between the e500 Core and the PowerQUICC III Core

Implementation (continued)

Feature

PowerQUICC Implementation

MPC8540 Datasheet(PDF) 248 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 248 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL