MFS5600AMBA0ES datasheet(109/111 Pages) NXP

109 / 111 page

NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

Fig. 10.

DCR current sense with a single capacitor ......22

Fig. 11.

Clock management system high-level block

diagram ............................................................29

Fig. 12.

Windowed watchdog concept ..........................40

Fig. 13.

Challenger watchdog formula ..........................42

Fig. 14.

Watchdog error counter configurations ............43

Fig. 15.

Watchdog refresh counter configurations ........ 44

Fig. 16.

FCCU 1/2 bi-stable protocol example ............. 44

Fig. 17.

Low-level ERRMONx detected as error .......... 46

Fig. 18.

8-bit CRC Polynomial ......................................49

Fig. 19.

FS5600 state diagram .....................................54

Fig. 20.

SW1 Soft-start .................................................85

Fig. 21.

SW1 Load Transient Response ...................... 86

Fig. 22.

SW2 Load Transient Response ...................... 86

Fig. 23.

SW1 Dropout Performance ............................. 87

Fig. 24.

SW2 Dropout Performance ............................. 87

Fig. 25.

SW1 Efficiency (12 Vin, 450 kHz) ................... 87

Fig. 26.

SW2 Efficiency (12 Vin, 450 kHz) ................... 88

Fig. 27.

SW1 Efficiency (5 Vout, 450 kHz) ................... 88

Fig. 28.

SW2 Efficiency (5 Vout, 450 kHz) ................... 88

Fig. 29.

SW1 Load Regulation ..................................... 89

Fig. 30.

SW2 Load Regulation ..................................... 89

Fig. 31.

Typical application block diagram ....................90

Fig. 32.

Example power up and power down

waveforms ....................................................... 91

Fig. 33.

Typical application schematic ..........................92

Fig. 34.

Package outline HVQFN32

(SOT617-24(SC)) – ES version (wettable

flank) ................................................................93

Fig. 35.

Package outline detail HVQFN32

(SOT617-24(SC)) – ES version (wettable

flank) ................................................................94

Fig. 36.

PCB design guidelines – solder

mask opening pattern for HVQFN32

(SOT617-24(SC)) – ES version (wettable

flank) ................................................................95

Fig. 37.

PCB guidelines – I/O pads and solderable

area for HVQFN32 (SOT617-24(SC)) – ES

version (wettable flank) ................................... 96

Fig. 38.

PCB design guidelines – solder paste

stencil for HVQFN32 (SOT617-24(SC)) –

ES version (wettable flank) ............................. 97

Fig. 39.

Package outline note HVQFN32

(SOT617-24(SC)) – ES version (wettable

flank) ................................................................98

Fig. 40.

Package outline HVQFN32

(SOT617-24(SC)) – EP version (non-

wettable flank) ................................................. 99

Fig. 41.

Package outline detail HVQFN32

(SOT617-24(SC)) – EP version (non-

wettable flank) ............................................... 100

Fig. 42.

PCB design guidelines – solder

mask opening pattern for HVQFN32

(SOT617-24(SC)) – EP version (non-

wettable flank) ............................................... 101

Fig. 43.

PCB guidelines – I/O pads and solderable

area for HVQFN32 (SOT617-24(SC)) – EP

version (non-wettable flank) .......................... 102

Fig. 44.

PCB design guidelines – solder paste

stencil for HVQFN32 (SOT617-24(SC)) –

EP version (non-wettable flank) .................... 103

Fig. 45.

Package outline note HVQFN32

(SOT617-24(SC)) – EP version (non-

wettable flank) ............................................... 104

FS5600

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Product data sheet

Rev. 3 — 2 August 2022

109 / 111

MFS5600AMBA0ES Datasheet(PDF) 109 Page - NXP Semiconductors

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