TPS3840PL33DBVR datasheet(4/46 Pages) TI

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RESET

VDD

GND

Not to scale

/ NC

RESET

VDD

GND

Not to scale

/ NC

TPS3840

SNVSB03D – DECEMBER 2018 – REVISED JANUARY 2020

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Product Folder Links: TPS3840

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6 Pin Configuration and Functions

DBV Package

5-Pin SOT-23

TPS3840PL, TPS3840DL Top View

DBV Package

5-Pin SOT-23

TPS3840PH Top View

Pin Functions

I/O

DESCRIPTION

NAME

TPS3840PL,

TPS3840DL

TPS3840PH

RESET

N/A

Active-High Output Reset Signal: This pin is asserted to logic high when either

the MR pin is pulled to a logic low or VDD voltage falls below the negative

voltage threshold (VIT-). When both MR is floating or above VMR_H and VDD

voltage rises above VIT+, RESET remains asserted to logic high (asserted) for

the reset time delay (tD) before releasing back to logic low.

RESET

N/A

Active-Low Output Reset Signal: This pin is asserted to logic low when either

the MR pin is pulled to a logic low or the VDD voltage falls below the negative

voltage threshold (VIT-). When both MR is floating or above VMR_H and VDD

voltage rises above VIT+, RESET remains asserted to logic low for the reset time

delay (tD) before releasing back to logic high.

VDD

Input Supply Voltage. TPS3840 monitors VDD voltage

GND

Ground

MR / NC

Manual Reset. Pull this pin to a logic low (VMR_L) to assert a reset signal at the

RESET/RESET pin. If the MR pin is left floating or pulled to VMR_H, the output

releases to the nominal state after the reset time delay (tD) expires. MR can be

left floating when not in use. NC stands for "No Connection" or floating.

Capacitor Time Delay Pin. The CT pin offers a user-programmable reset delay

time. Connect an external capacitor on this pin to adjust the reset time delay.

When not in use, leave pin floating for the smallest fixed reset time delay.

TPS3840PL33DBVR Datasheet(PDF) 4 Page - Texas Instruments

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