TPS3840PL33DBVR datasheet(21/46 Pages) TI

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VDD

RESET

(LDO Enable)

(LDO)

OUT

30ms delay from VDD (3.3V) to LDO Enable set by 0.047µF on CT of TPS3840PL30

Negligible delay from LDO Enable to 1.8V VOUT

TPS3840

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SNVSB03D – DECEMBER 2018 – REVISED JANUARY 2020

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Typical Application (continued)

9.2.1.1 Design Requirements

This design requires voltage supervision on two separate rails: 3.3-V and 1.8-V rails. The voltage rail needs to

sequence upon power up with the 3.3-V rail coming up first followed by the 1.8-V rail at least 25 ms after.

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Two Rail Voltage Supervision

Monitor 3.3-V and 1.8-V rails

Two TPS3840 devices provide voltage monitoring

with 1% accuracy with device options available in

0.1 V variations

Voltage Rail Sequencing

Power up the 3.3-V rail first followed by 1.8-V rail

25 ms after

The CT capacitor on TPS38240PL28 is set to

0.047 µF for a reset time delay of 29 ms typical

Output logic voltage

3.3-V Open-Drain

Maximum device current

consumption

1 µA

Each TPS3840 requires 350 nA typical

9.2.1.2 Detailed Design Procedure

The primary constraint for this application is choosing the correct device to monitor the supply voltage of the

microprocessor. The TPS3840 can monitor any voltage between 1.6 V and 10 V and is available in 0.1 V

increments. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to

trigger determines the correct voltage supervisor variant to choose. In this example, the first TPS3840 triggers

when the 3.3-V rail falls to 3.0 V. The second TPS3840 triggers a reset when the 1.8-V rail falls to 1.6 V. The

secondary constraint for this application is the reset time delay that must be at least 25 ms to allow the

microprocessor, and all other devices using the 3.3-V rail, enough time to startup correctly before the 1.8-V rail is

enabled via the LDO. Because a minimum time is required, the user must account for capacitor tolerance. For

applications with ambient temperatures ranging from –40°C to +125°C, CCT can be calculated using RCT and

solving for CCT in Equation 2. Solving Equation 2 for 25 ms gives a minimum capacitor value of 0.04 µF which is

rounded up to a standard value 0.047 µF to account for capacitor tolerance.

A 1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor

is only required for the Open-Drain device variants and is calculated to maintain the RESET current within the ±5

mA limit found in the Recommended Operating Conditions: RPull-up = VPull-up ÷ 5 mA. For this design, a standard

10-k

Ω pull-up resistor is selected to minimize current draw when RESET is asserted. Keep in mind the lower the

pull-up resistor, the higher VOL. The MR pin can be connected to an external signal if desired or left floating if not

used due to the internal pull-up resistor to VDD.

9.2.1.3 Application Curves

Figure 49. Startup Sequence Highlighting the Delay Between 3.3V and 1.8V Rails

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