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TPS3840PL33DBVR Datasheet(PDF) 13 Page - Texas Instruments |
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TPS3840PL33DBVR Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 46 page ![]() Overdrive (%) 5 10 15 20 25 30 35 40 45 50 12 13 14 15 16 17 18 19 20 21 22 Glit 25°C -40°C 125°C Temperature (°C) -40 -20 0 20 40 60 80 100 120 140 458 460 462 464 466 468 470 472 474 476 478 RCTv DL49 PL49 PH49 Temperature (°C) -40 -20 0 20 40 60 80 100 120 140 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 MR_H PL16 PL28 PL49 Temperature (°C) -40 -20 0 20 40 60 80 100 120 140 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 MR_H PH16 PH30 PH49 Temperature (°C) -40 -20 0 20 40 60 80 100 120 140 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 MR_L PH16 PH230 PH49 Temperature (°C) -40 -20 0 20 40 60 80 100 120 140 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 MR_H DL16 DL29 DL49 13 TPS3840 www.ti.com SNVSB03D – DECEMBER 2018 – REVISED JANUARY 2020 Product Folder Links: TPS3840 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Typical Characteristics (continued) Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpull- up = 100 kΩ, CLoad = 50 pF, unless otherwise noted. Figure 31. Manual Reset Logic Low Voltage Threshold over Temperature for TPS3840PHXX Figure 32. Manual Reset Logic High Voltage Threshold over Temperature for TPS3840DLXX Figure 33. Manual Reset Logic High Voltage Threshold over Temperature for TPS3840PLXX Figure 34. Manual Reset Logic High Voltage Threshold over Temperature for TPS3840PHXX Figure 35. Glitch Immunity on VIT- vs Overdrive (Data Taken with TPS3840PL28) Figure 36. CT Pin Internal Resistance over Temperature |
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