TPS3840PL33DBVR datasheet(18/46 Pages) TI

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VIT+

tP_HL

VHYS

VIT+

VHYS

VIT-

tMR_tD

VMR_L

tMR_RES

tMR_PW

Reset not asserted

Pulse width less than

tMR_PW

RESET

VDD

VMR_H

VIT-

TPS3840

SNVSB03D – DECEMBER 2018 – REVISED JANUARY 2020

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Feature Description (continued)

The recommended maximum delay capacitor for the TPS3840 is limited to 10 µF as this ensures there is enough

time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the

previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before

the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero

volts and the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the

capacitor has enough time to fully discharge during the duration of the voltage fault.

8.3.3 Manual Reset (MR) Input

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR

with pulse duration longer than tMR_RES will causes reset output to assert. After MR returns to a logic high (VMR_H)

and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.

If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than

VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to

either VDD or GND. VMR should not be higher than VDD voltage.

Figure 47. Timing Diagram MR and RESET (TPS3840DL)

8.3.4 Output Logic

8.3.4.1 RESET Output, Active-Low

RESET (Active-Low) applies to TPS3840DL (Open-Drain) and TPS3840PL (Push-Pull) hence the "L" in the

device name. RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT-) and the

MR pin is floating or above VMR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then

RESET is asserted.

When MR is again logic high or floating and VDD rise above VIT+, the delay circuit will hold RESET low for the

specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic high

voltage (VOH).

The TPS3840DL (Open-Drain) version, denoted with "D" in the device name, requires a pull-up resistor to hold

RESET pin high. Connect the pull-up resistor to the desired pull-up voltage source and RESET can be pulled up

to any voltage up to 10 V independent of the VDD voltage. To ensure proper voltage levels, give some

consideration when choosing the pull-up resistor values. The pull-up resistor value determines the actual VOL, the

output capacitive loading, and the output leakage current (ILKG(OD)).

The Push-Pull variants (TPS3840PL and TPS3840PH), denoted with "P" in the device name, does not require a

pull-up resistor

TPS3840PL33DBVR Datasheet(PDF) 18 Page - Texas Instruments

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