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LPC55S2X Datasheet(PDF) 3 Page - NXP Semiconductors

Part # LPC55S2X
Description  32-bit Arm Cortex®-M33, CASPER, 256 KB SRAM; 512 KB flash, USB HS, Flexcomm Interface, SDIO, 32-bit counter/ timers, SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC, Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG
PDF  140 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC55S2X Datasheet(HTML) 3 Page - NXP Semiconductors

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LPC55S2x/LPC552x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2022. All rights reserved.
Product data sheet
Rev. 2.2 — 8 December 2022
3 of 139
NXP Semiconductors
LPC55S2x/LPC552x
32-bit ARM Cortex-M33 microcontroller
Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.
SDIO with support for up to two cards. Supported card types are MMC, SDIO, and
CE-ATA. Supports SD2.0, and SDR25 (52MHz).
CRC engine block can calculate a CRC on supplied data using one of three
standard polynomials with DMA support.
Up to 64 General-Purpose Input/Output (GPIO) pins.
GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,
falling or both input edges.
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
I/O pin configuration with support for up to 16 function options.
Programmable Logic Unit (PLU) to create small combinatorial and/or sequential
logic networks including state machines.
Security Features:
AES-256 encryption/decryption engine with keys fed directly from PUF or a
software supplied key
Secure Hash Algorithm (SHA2) module supports secure boot with dedicated DMA
controller.
Physical Unclonable Function (PUF) using dedicated SRAM for silicon fingerprint.
PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes
hardware for key extraction.
True Random Number Generator (TRNG).
128 bit unique device serial number for identification (UUID).
Secure GPIO.
Timers:
Five 32-bit standard general purpose asynchronous timers/counters, which support
up to four capture inputs and four compare outputs, PWM mode, and external
count input. Specific timer events can be selected to generate DMA requests.
One SCTimer/PWM with 8 input and 10 output functions (including 16 capture and
match registers). Inputs and outputs can be routed to or from external pins and
internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16
captures/matches, 16 events, and 32 states.
32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. Another timer in the RTC can be used for wake-up from all low power
modes including deep power-down, with 1 ms resolution. The RTC is clocked by
the 32 kHz FRO or 32.768 kHz external crystal.
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
Windowed Watchdog Timer (WWDT) with FRO 1 MHz as clock source.
The Micro-Tick Timer running from the watchdog oscillator can be used to wake-up
the device from sleep and deep-sleep modes. Includes 4 capture registers with pin
inputs.
42-bit free running OS Timer as continuous time-base for the system, available in
any reduced power modes. It runs on 32kHz clock source, allowing a count period
of more than 4 years.



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