ST25DV04K datasheet(64/197 Pages) STMICROELECTRONICS

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6.3

Device addressing

To start a communication between the bus master and the slave device, the bus master must initiate a Start

condition. Following this, the bus master sends the device select code, shown in Table 88. Device select code (on

Serial Data (SDA), the most significant bit first).

The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable “Address” (E2,1,1). To

address the memory array, the 4-bit device type identifier is 1010b. Refer to Table 88. Device select code.

The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.

Table 88. Device select code

Device type identifier (1)

Chip Enable address

Device select code

E2(2)

1. The most significant bit, b7, is sent first.

2. E2 is not connected to any external pin. It is however used to address the ST25DVxxx as described in Section 4 Memory

management.

•

E2 = 0, access to user memory, Dynamic registers or Mailbox.

•

E2 =1, access to system area.

If a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data

(SDA) during the ninth bit time. If the device does not match the device select code, it deselects itself from the

bus, and goes into Standby mode.

Table 89. Operating modes

Mode

RW bit

Bytes

Initial sequence

Current address read

Start, device select, RW = 1

Random address read

Start, device select, RW = 0, address

reStart, device select, RW = 1

Sequential read

≥ 1

Similar to current or random address read

Byte write

Start, device select, RW = 0

Sequential write

≤ 256 byte

Start, device select, RW = 0

6.4

I2C write operations

Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0.

The device acknowledges it, and waits for two address bytes. The device responds to each address byte with an

acknowledge bit, and then waits for the data byte.

Each data byte in the memory has a 16-bit (two-byte wide) address. The most significant byte (see Table 90)

is sent first, followed by the least significant byte (see Table 91). Bits b15 to b0 form the address of the byte in

memory.

Table 90. Address most significant byte

b15

b14

b13

b12

b11

b10

Table 91. Address least significant byte

When the bus master generates a Stop condition immediately after the Ack bit (in the tenth-bit time slot), either at

the end of a byte write or a sequential write, the internal write cycle is triggered. A Stop condition at any other time

slot does not trigger the internal write cycle.

ST25DV04K ST25DV16K ST25DV64K

Device addressing

DS10925 - Rev 11

page 64/197

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