HC705RC16GRSSLASHD datasheet(23/120 Pages) NXP

23 / 120 page

General Description

Signal Description

MC68HC705RC16 — Rev. 3.0

General Release Specification

General Description

1.5.7 PA0–PA7

These eight I/O lines comprise port A. The state of any pin is software

programmable and all port A lines are configured as inputs during

power-on or reset. For detailed information on I/O programming, see 2.4

Input/Output Programming.

1.5.8 PB0–PB7

These eight I/O lines comprise port B. The state of any pin is software

programmable and all port B lines are configured as inputs during

power-on or reset. Each port B I/O line has a mask optionable

pullup/interrupt for keyscan. For detailed information on I/O

programming, see 2.4 Input/Output Programming.

1.5.9 PC0–PC3 (PC4–PC7)

These eight I/O lines comprise port C. PC0 is a high-current pin.

PC4–PC7 are available only in the 44-lead PLCC package. The state of

any pin is software programmable and all port C lines are configured as

input during power-on or reset. For detailed information on I/O

programming, see 2.4 Input/Output Programming.

NOTE:

Only four bits of port C are bonded out in 28-pin packages for the

MC68HC705RC16, although port C is truly an 8-bit port. Since pins

PC4–PC7 are unbonded, software should include the code to set their

respective data direction register locations to outputs to avoid floating

inputs.

NOTE:

Any unused inputs, I/O ports, and no connects should be tied to an

appropriate logic level (either VDD or VSS). Although the I/O ports of the

MC68HC705RC16 do not require termination, termination is

recommended to reduce the possibility of static damage.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705RC16GRS/D Datasheet(PDF) 23 Page - NXP Semiconductors