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HC705RC16GRS/D Datasheet(PDF) 62 Page - NXP Semiconductors |
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HC705RC16GRS/D Datasheet(HTML) 62 Page - NXP Semiconductors |
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62 / 120 page  Core Timer General Release Specification MC68HC705RC16 — Rev. 3.0 Core Timer TOFC — Timer Overflow Flag Clear When a one is written to this bit, CTOF is cleared. Writing a zero has no effect on the CTOF bit. This bit always reads as zero. RTFC — Real-Time Interrupt Flag Clear When a one is written to this bit, RTIF is cleared. Writing a zero has no effect on the RTIF bit. This bit always reads as zero. RT1 and RT0 — Real-Time Interrupt Rate Select These two bits select one of four taps from the real-time interrupt circuit. Refer to Table 8-1. Reset sets these two bits which selects the lowest periodic rate and gives the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the timeout period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing RTI taps. Table 8-1. RTI and COP Rates at 4.096 MHz Oscillator RTI RATE 2.048-MHz Bus RT1:RT0 MINIMUM COP RATES 2.048-MHz Bus 2 ms 212 ÷ E 00 (215–212)/E 14 ms 4 ms 213 ÷ E 01 (216–213)/E 28 ms 8 ms 214 ÷ E 10 (217–214)/E 56 ms 16 ms 215 ÷ E 11 (218–215)/E 112 ms Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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